ST10F296 datasheet(102/346 Pages) STMICROELECTRONICS

102 / 346 page

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Interrupt system

ST10F296E

102/346

Hardware traps are exceptions or error conditions that arise during run-time. They cause

immediate non-maskable system reactions similar to a standard interrupt service (branching

to a dedicated vector table location).

The occurrence of a hardware trap is signified by an individual bit in the trap flag register

(TFR). Except when another higher prioritized trap service is in progress, a hardware trap

interrupts any other program execution. Hardware trap services cannot be interrupted by a

standard or PEC interrupt.

CAPCOM timer 7

T7IR

T7IE

T7INT

00’00F4h

3Dh

CAPCOM timer 8

T8IR

T8IE

T8INT

00’00F8h

3Eh

GPT1 timer 2

T2IR

T2IE

T2INT

00’0088h

22h

GPT1 timer 3

T3IR

T3IE

T3INT

00’008Ch

23h

GPT1 timer 4

T4IR

T4IE

T4INT

00’0090h

24h

GPT2 timer 5

T5IR

T5IE

T5INT

00’0094h

25h

GPT2 timer 6

T6IR

T6IE

T6INT

00’0098h

26h

GPT2 CAPREL register

CRIR

CRIE

CRINT

00’009Ch

27h

ADC complete

ADCIR

ADCIE

ADCINT

00’00A0h

28h

ADC overrun error

ADEIR

ADEIE

ADEINT

00’00A4h

29h

ASC0 transmit

S0TIR

S0TIE

S0TINT

00’00A8h

2Ah

ASC0 transmit buffer

S0TBIR

S0TBIE

S0TBINT

00’011Ch

47h

ASC0 receive

S0RIR

S0RIE

S0RINT

00’00ACh

2Bh

ASC0 error

S0EIR

S0EIE

S0EINT

00’00B0h

2Ch

SSC transmit

SCTIR

SCTIE

SCTINT

00’00B4h

2Dh

SSC receive

SCRIR

SCRIE

SCRINT

00’00B8h

2Eh

SSC error

SCEIR

SCEIE

SCEINT

00’00BCh

2Fh

PWM channel 0...3

PWMIR

PWMIE

PWMINT

00’00FCh

3Fh

See Section 9.1

XP0IR

XP0IE

XP0INT

00’0100h

40h

See Section 9.1

XP1IR

XP1IE

XP1INT

00’0104h

41h

See Section 9.1

XP2IR

XP2IE

XP2INT

00’0108h

42h

See Section 9.1

XP3IR

XP3IE

XP3INT

00’010Ch

43h

Table 47.

Interrupt sources (continued)

Source of Interrupt or

PEC service request

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

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