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ST10F296 数据表(PDF) 105 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Interrupt system 105/346 9.2 Exception and error traps list Table 49 shows all of the possible exceptions or error conditions that can arise during run- time. Table 49. Trap priorities Exception condition Trap flag Trap vector Vector location Trap number Trap priority(1) 1. All class B traps have the same trap number, trap vector, and lower priority compared to class A traps and resets. Each class A trap has a dedicated trap number (and vector). They are prioritized in the second priority level. Resets have the highest priority level and the same trap number. The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced. Reset functions: Hardware reset Software reset Watchdog timer overflow RESET RESET RESET 00’0000h 00’0000h 00’0000h 00h 00h 00h III III III Class A hardware traps: Nonmaskable interrupt Stack overflow Stack underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008h 00’0010h 00’0018h 02h 04h 06h II II II Class B hardware traps: Undefined opcode MAC Interruption Protected instruction fault Illegal word operand access Illegal instruction access Illegal external bus access UNDOPC MACTRP PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028h 00’0028h 00’0028h 00’0028h 00’0028h 00’0028h 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah I I I I I I Reserved [002Ch - 003Ch] [0Bh - 0Fh] Software traps: TRAP Instruction Any 0000h – 01FCh in steps of 4h Any [00h - 7Fh] Current CPU priority Obsolete Product(s) - Obsolete Product(s) |
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