ST10F296 datasheet(108/346 Pages) STMICROELECTRONICS

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Capture/compare (CAPCOM) units

ST10F296E

108/346

Figure 23.

Block diagram of CAPCOM timers T1 and T8

Note:

When an external input signal is connected to the input lines of both T0 and T7, these timers

count the input signal synchronously. Thus, the two timers can be regarded as one timer

whose contents can be compared with 32 capture registers.

When a capture/compare register has been selected for capture mode, the current contents

of the allocated timer are latched (captured) into the capture/compare register in response

to an external event at the port pin which is associated with this register. In addition, a

specific interrupt request for this capture/compare register is generated.

Either a positive, a negative, or both a positive and a negative external signal transition at

the pin can be selected as the triggering event. The contents of all registers which have

been selected for one of the five compare modes are continuously compared with the

contents of the allocated timers.

When a match occurs between the timer value and the value in a capture/compare register,

specific actions are taken based on the selected compare mode (see Table 50).

The input frequencies fTx, for the timer input selector Tx, are determined as a function of the

CPU clocks. The timer input frequencies, resolution and periods which result from the

selected prescaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in

Table 51 and Table 52 respectively.

The numbers for the timer periods are based on a reload value of 0000h. Note that some

numbers may be rounded to three significant figures.

Txl

CPU

clock

TxR

MUX

GPT2 timer T6

over/underflow

TxM

Reload register TxREL

CAPCOM timer Tx

TxIR

Interrupt

request

x = 1. 8

Table 50.

Compare modes

Function

Mode 0

Interrupt-only compare mode

Several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match

Several compare events per timer period are possible

Mode 2

Interrupt-only compare mode

Only one compare interrupt per timer period is generated

Mode 3

Pin set to 1 on match

pin reset to 0 on compare time overflow

Only one compare event per timer period is generated

Double register mode

Two registers operate on one pin

Pin toggles on each compare match

Several compare events per timer period are possible

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