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ST10F296 数据表(PDF) 142 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 142 Page - STMicroelectronics |
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142 / 346 page  Obsolete Product(s) - Obsolete Product(s) Parallel ports ST10F296E 142/346 Figure 40. Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) 13.6 Port 4 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. 13.6.1 Port 4 registers P4 register Only bits 7 to 0 of the P4 register are implemented. All other bits are read as 0. Direction latch Write DP3.x Read DP3.x Port output latch Write P3.x Read P3.x MUX 0 1 MUX 0 1 Alternate data output MUX 0 1 1 Input latch Clock P3.12/BHE P3.15/CLKOUT Output buffer x = 15, 12 Alternate function enable P4 (FFC8h/E4h) SFR Reset value: --00h 15 14 13 12 11 10 987 65432 10 --- ----- P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 --- ----- RW RW RW RW RW RW RW RW Table 81. P4 register description Bit Bit name Function 7-0 P4.y Port data register P4 bit y Obsolete Product(s) - Obsolete Product(s) |
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