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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST10F296 数据表(PDF) 213 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 213 Page - STMicroelectronics |
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213 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Watchdog timer 213/346 If a bidirectional reset is enabled, and if the RSTIN pin is latched low at the end of an internal reset sequence, a short hardware reset, a software reset or a watchdog reset triggers a long hardware reset. Thus, reset indications flags are set to indicate a long hardware reset. The watchdog timer is 16-bits in length and is clocked with the system clock divided by 2 or 128. The high byte of the watchdog timer register can be set to a prespecified reload value (stored in WDTREL). Each time the high byte of the watchdog timer is serviced by the application software, it is reloaded. For security reasons, the WDTCON register should be rewritten each time before the watchdog timer is serviced Table 129 and Table 130 show the watchdog time range for 40 MHz and 64 MHz CPU clock respectively. The watchdog timer period is calculated using the following formula: Equation 21 Table 129. WDTREL reload value (fCPU = 40 MHz) Reload value in WDTREL Prescaler for fCPU = 40 MHz 2 (WDTIN = 0) 128 (WDTIN = 1) FFh 12.8 µs 819.2 µs 00h 3.277 ms 209.7 ms Table 130. WDTREL reload value (fCPU = 64 MHz) Reload value in WDTREL Prescaler for fCPU = 64 MHz 2 (WDTIN = 0) 128 (WDTIN = 1) FFh 8 µs 512 µs 00h 2.048 ms 131.1 ms P WDT 1f CPU ⁄ 512 1 WDTIN [] 63 × + () 256 WDTREL [] – () × × × = Obsolete Product(s) - Obsolete Product(s) |
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