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ST10F296 数据表(PDF) 225 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 225 Page - STMicroelectronics |
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225 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E System reset 225/346 Figure 81. Synchronous long hardware reset (EA = 1) 1. If RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation) during the reset condition ( RSTIN low), an asynchronous reset is entered immediately. Even if RPD returns above teh threshold, the reset is taken as asychronous. 2. The minimum RSTIN low pulse duration must be longer than 500 ns, to guarantee the pulse is not masked by the internal filter (see Section 21.1: Idle mode on page 240). P0[15:13] Not transparent RSTF P0[12:2] Transparent Not t. P0[1:0] Not t. Not transparent FLARST RST ≤1 ms 1024+8 TCL ≤2 TCL (1) V RPD > 2.5 V asynchronous reset not entered 200 mA discharge RPD RSTOUT At this time RSTF is sampled low so it is definitely a long reset (after filter) RSTIN 1024+8 TCL ≤4 TCL(2) ≤12 TCL ≤500 ns ≥ 50 ns ≤500 ns ≥ 50 ns ≤500 ns ≥ 50 ns IBUS-CS 7 TCL Not t. Transparent Not t. 3..4 TCL (internal) Obsolete Product(s) - Obsolete Product(s) |
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