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ST10F296 数据表(PDF) 313 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 313 Page - STMicroelectronics |
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313 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Electrical characteristics 313/346 Figure 104. Generation mechanisms for the CPU clock 24.8.3 Clock generation modes Figure 168 associates combinations of the P0.15-13 (P0H.7-5) bits with the respective clock generation mode. The external clock input range refers to a CPU clock range of 1 to 64 MHz. In addition, PLL use is limited to 4-12 MHz input frequency range. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from direct drive). On the contrary, the clock can be forced through an external clock source only in direct drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can be used). TCL TCL TCL TCL fCPU fXTAL fCPU fXTAL PLL operation Direct clock drive TCL TCL fCPU fXTAL Prescaler operation Table 168. On-chip clock generator selections P0.15-13 (P0H.7-5) CPU frequency fCPU = fXTAL x F External clock input range Notes 11 1 FXTAL x 4 4 to 8 MHz Default configuration 11 0 FXTAL x 3 5.3 to 10.6 MHz 10 1 FXTAL x 8 4 to 8 MHz 10 0 FXTAL x 5 6.4 to 12 MHz 01 1 FXTAL x 1 1 to 64 MHz Direct drive (oscillator bypassed)(1) 1. The maximum frequency of the external clock depends on the duty cycle of the external clock signal. When 64 MHz is used, 50 % duty cycle is granted (low phase = high phase = 7.8 ns). When 32 MHz is selected, a 25 % duty cycle can be accepted (minimum, high or low phase = 7.8 ns). 01 0 FXTAL x 10 4 to 6.4 MHz 00 1 FXTAL/2 4 to 12 MHz CPU clock via prescaler(1) 00 0 FXTAL x 16 4 MHz Obsolete Product(s) - Obsolete Product(s) |
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