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ST10F296 数据表(PDF) 322 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 322 Page - STMicroelectronics |
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322 / 346 page  Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST10F296E 322/346 24.8.16 External memory bus timing The next sections, Multiplexed bus timings and Demultiplexed bus timings, describe the external memory bus timings. The given values are computed for a maximum CPU clock of 40 MHz. It is clear that when a higher CPU clock frequency is used (up to 64 MHz), some numbers in the timing formulas become zero or negative, which in most cases is not acceptable or meaningful. In these cases, the speed of the bus settings tA, tC and tF must be correctly adjusted. Note: All external memory bus timings and SSC timings presented in the following tables are given by design characterization and not fully tested in production. Multiplexed bus timings VDD = 5 V ±10 %, VSS = 0 V, TA = -40 to 125 °C, CL = 50 pF, ALE cycle time = 6 TCL + 2tA + tC + tF (75 ns at 40 MHz CPU clock without wait states). Table 175. Multiplexed bus timings Symbol Parameter FCPU = 40 MHz TCL = 12.5 ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Unit Min Max Min Max t5 (CC) ALE high time 4 + tA - TCL - 8.5 + tA - ns t6 (CC) Address setup to ALE 1.5 + tA TCL - 11 + tA t7 (CC) Address hold after ALE 4 + tA TCL - 8.5 + tA t8 (CC) ALE falling edge to RD, WR (with R/W delay) 4 + tA TCL - 8.5 + tA t9 (CC) ALE falling edge to RD and WR (no R/W delay) -8.5 + tA -8.5 + tA t10 (CC) Address float after RD and WR (with R/W delay)(1) - 6 - 6 t11 (CC) Address float after RD and WR (no R/W delay)(1) 18.5 TCL + 6 t12 (CC) RD and WR low time (with R/W delay) 15.5 + tC - 2TCL - 9.5 + tC - t13 (CC) RD and WR low time (no R/W delay) 28 + tC 3TCL - 9.5 + tC t14 (SR) RD to valid data in (with R/W delay) - 6 + tC - 2TCL - 19 + tC t15 (SR) RD to valid data in (no R/W delay) 18.5 + tC 3TCL - 19 + tC t16 (SR) ALE low to valid data in 17.5 + tA + tC 3TCL - 20 + tA + tC t17 (SR) Address/unlatched CS to valid data in 20 + 2tA + tC 4TCL - 30 + 2tA + tC t18 (SR) Data hold after RD rising edge 0 - 0 - Obsolete Product(s) - Obsolete Product(s) |
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