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ST10F296 数据表(PDF) 334 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 334 Page - STMicroelectronics |
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334 / 346 page  Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST10F296E 334/346 24.8.17 READY and CLKOUT VDD = 5 V ±10 %, VSS = 0 V, TA = -40 to 125°C, CL = 50 pF. Table 177. READY and CLKOUT Symbol Parameter FCPU = 40 MHz TCL = 12.5 ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Unit Min Max Min Max t29 (CC) CLKOUT cycle time 25 25 2 TCL 2 TCL ns t30 (CC) CLKOUT high time 9 - TCL - 3.5 - t31 (CC) CLKOUT low time 10 TCL - 2.5 t32 (CC) CLKOUT rise time -4 - 4 t33 (CC) CLKOUT fall time t34 (CC) CLKOUT rising edge to ALE falling edge -2 + tA 8 + tA -2 + tA 8 + tA t35 (SR) Synchronous READY setup time to CLKOUT 17 - 17 - t36 (SR) Synchronous READY hold time after CLKOUT 22 t37 (SR) Asynchronous READY low time 35 2 TCL + 10 t58 (SR) Asynchronous READY setup time(1) 1. These timings are given for characterization purposes only, to assure recognition at a specific clock edge. 17 17 t59 (SR) Asynchronous READY hold time(1) 22 t60 (SR) Asynchronous READY hold time after RD and WR high (demultiplexed bus)(2) 2. Demultiplexed bus is the worst case scenario. For a multiplexed bus, 2TCLs must be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the next bus cycle and tF refers to the current bus cycle. 02tA + tC + tF 02tA + tC + tF Obsolete Product(s) - Obsolete Product(s) |
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