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ST7DALIF2 数据表(PDF) 138 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 138 Page - STMicroelectronics |
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138 / 171 page  Electrical characteristics ST7DALIF2 138/171 20.5 Clock and timing characteristics Subject to general operating conditions for VDD, fOSC, and TA. 20.5.1 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with eight different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Table 74. General timings Symbol Parameter (1) 1. Guaranteed by design. Not tested in production. Conditions Min Typ (2) 2. Data based on typical application software. Max Unit tc(INST) Instruction cycle time fCPU=8 MHz 23 12 t CPU 250 375 1500 ns tv(IT) Interrupt reaction time (3) tv(IT) = Δtc(INST) + 10 3. Time measured between interrupt event and interrupt vector fetch. Δt c(INST) is the number of tCPU cycles needed to finish the current instruction execution. fCPU=8 MHz 10 22 t CPU 1.25 2.75 μs Table 75. Auto wakeup from halt oscillator (AWU) Symbol Parameter (1) 1. Guaranteed by design. Conditions Min Typ Max Unit fAWU AWU Oscillator Frequency 50 125 250 kHz tRCSRT AWU Oscillator startup time 50 µs Table 76. Oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fCrOSC Crystal Oscillator Frequency (1) 1. When PLL is used, please refer to the PLL characteristics chapter and to Section 9: Supply, reset and clock management on page 32 (fCrOSC min. is 8 MHz with PLL). 216 MHz CL1 CL2 Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS) See table below pF |
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