ST7DALIF2 datasheet(149/171 Pages) STMICROELECTRONICS

149 / 171 page

ST7DALIF2

Electrical characteristics

149/171

20.9

Control pin characteristics

TA = -40°C to 85°C, unless otherwise specified

Table 87.

Asynchronous RESET pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

VSS - 0.3

0.3xVDD

VIH

Input high level voltage

0.7xVDD

VDD + 0.3

Vhys

Schmitt trigger voltage

hysteresis (1)

VOL

Output low level voltage (2)

VDD=

5 V

IIO=+5 mA TA≤85° C

TA≥85° C

0.5

1.0

1.2

IIO=+2 mA TA≤85° C

TA≥85° C

0.2

0.4

0.5

RON

Pull-up equivalent resistor (3) (1)

VDD=5 V

VDD=3 V

120

tw(RSTL)o

Generated reset pulse duration Internal reset sources

μs

th(RSTL)in

External reset pulse hold time

(4)

μs

tg(RSTL)in Filtered glitch duration

200

Data based on characterization results, not tested in production.

The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O

ports and control pins) must not exceed IVSS.

The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax

and VDD

To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

ST7DALIF2 数据表(PDF) 149 Page - STMicroelectronics

ST7DALIF2 数据表(HTML) 149 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载