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ST7DALIF2 数据表(PDF) 152 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 152 Page - STMicroelectronics

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Electrical characteristics
ST7DALIF2
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Figure 89.
SPI slave timing diagram with CPHA=0
Note:
1
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2
When no communication is on-going the data output line of the SPI (MOSI in master mode,
MISO in slave mode) has its alternate function capability released. In this case, the pin
status depends on the I/O port configuration.
tsu(SS)
(1) SS setup time (2)
Slave
(4 x TCPU) +150
ns
th(SS)
(1)
SS hold time
Slave
120
tw(SCKH)
tw(SCKL)
SCK high and low
time
Master
Slave
100
90
tsu(MI)
tsu(SI)
Data input setup time
Master
Slave
100
100
th(MI)
th(SI)
Data input hold time
Master
Slave
100
100
ta(SO)
Data output access
time
Slave
0
120
tdis(SO)
Data output disable
time
Slave
240
tv(SO)
Data output valid
time
Slave (after enable
edge)
120
th(SO)
Data output hold time
0
tv(MO)
Data output valid
time
Master (after enable
edge)
120
th(MO)
Data output hold time
0
1.
Data based on design simulation and/or characterisation results, not tested in production.
2.
Depends on fCPU. For example, if fCPU = 8 MHz, then TCPU = 1/ fCPU = 125 ns and tSU(SS) = 550 ns
Table 88.
SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
SS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
see note 2
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
see
note 2
BIT1 IN



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