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ST7DALIF2 数据表(PDF) 156 Page - STMicroelectronics |
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ST7DALIF2 数据表(HTML) 156 Page - STMicroelectronics |
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156 / 171 page ![]() Electrical characteristics ST7DALIF2 156/171 Figure 94. ADC accuracy characteristics with amplifier enabled Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that fADC be less than or equal to 2 MHz. (if fCPU=8 MHz. then SPEED=0, SLOW=1). Figure 95. Amplifier output voltage vs. input voltage EO EG 1LSBIDEAL Vin (LSBIDEAL) Digital Result ADCDR 704 108 0 1 2345 67 701 702 703 704 (1) (2) ET ED EL (3) VSS 430mV 62.5mV Vin (OPAMP) Vin Vout (ADC input) Vmax Vmin 0V 430 mV 0V Noise (OPAMP input) |
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