ST7DALIF2 datasheet(154/171 Pages) STMICROELECTRONICS

154 / 171 page

Electrical characteristics

ST7DALIF2

154/171

20.11

10-bit ADC characteristics

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Figure 92.

Typical Application with ADC

Table 89.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ (1)

Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as

design guidelines and are not tested.

Max

Unit

fADC

ADC clock frequency

MHz

VAIN

Conversion voltage range (2)

When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

VSSA

VDDA

RAIN

External input resistor

10 (3)

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10k

Ω). Data based on characterization results, not tested in production.

CADC

Internal sample and hold

capacitor

6pF

tSTAB

Stabilization time after ADC

enable

fCPU=8MHz,

fADC=4MHz

0 (4)

The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable

is then always valid.

μs

tADC

Conversion time

(Sample+Hold)

3.5

- Sample capacitor loading

time

- Hold conversion time

1/fADC

IADC

Analog Part

Digital Part

0.2

AINx

ST72XXX

VDD

±1

μA

0.6V

CADC

6pF

VAIN

RAIN

10-Bit A/D

Conversion

CAIN

ST7DALIF2 数据表(PDF) 154 Page - STMicroelectronics

ST7DALIF2 数据表(HTML) 154 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载