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ST7DALIF2 数据表(PDF) 150 Page - STMicroelectronics

部件名 ST7DALIF2
功能描述  Configurable watchdog timer
PDF  171 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 数据表(HTML) 150 Page - STMicroelectronics

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Electrical characteristics
ST7DALIF2
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RESET pin protection when LVD is enabled
When the LVD is enabled, it is recommended to protect the RESET pin as shown in
Figure 87 and follow these guidelines:
1.
The reset network protects the device against parasitic resets.
2.
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
3.
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the VIL max. level specified in Section 20.8. Otherwise
the reset will not be taken into account internally.
4.
Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin (by an
external pull-up for example) is less than the absolute maximum value specified for
IINJ(RESET) in Section 20.2 on page 128.
5.
When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-
down capacitor is recommended to filter noise on the reset line.
6.
In case a capacitive power supply is used, it is recommended to connect a 1M ohm
pull-down resistor to the RESET pin to discharge any residual voltage induced by this
capacitive power supply (this will add 5 µA to the power consumption of the MCU).
Tips when using the LVD:
Check that all recommendations related to reset circuit have been applied (see section
above)
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1M Ohm
pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to
avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: Replace 10 nF pull-down on the RESET pin with a 5 µF to
20 µF capacitor.
Figure 87.
RESET pin protection when LVD is enabled.
0.01
μF
ST72XXX
PULSE
GENERATOR
Filter
RON
VDD
INTERNAL
RESET
RESET
EXTERNAL
Required
1M
Ω
Optional
WATCHDOG
LVD RESET
ILLEGAL OPCODE



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