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ST10F296 数据表(PDF) 116 Page - STMicroelectronics

部件名 ST10F296
功能描述  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F296 数据表(HTML) 116 Page - STMicroelectronics

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Pulse-width modulation (PWM) modules
ST10F296E
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XPWMPORT register
The XPWMPORT register is enabled and visible only when the XPEN and XPWMEN bits of
the SYSCON and XPERCON registers respectively are set.
12.2.1
Software control of the XPWM outputs
In an application, the XPWM output signals are generally controlled by the XPWM module.
However, it may be necessary to influence the level of the XPWM output pins via software,
either to initialize the system or to react to some extraordinary conditions such as a system
fault or an emergency.
Clearing the timer run bit PTRx stops the associated counter and leaves the respective
output at its current level.
The individual XPWM channel outputs are controlled by comparators according to the
formula:
PWM output signal = [XPTx] > [XPWx shadow latch]
Whenever software changes register XPTx, the respective output reflects the condition after
the change. Loading timer XPTx with a value greater than or equal to the value in XPWx
immediately sets the respective output, an XPTx value below the XPWx value clears the
respective output.
By clearing or setting the respective XPWMPORT output latch the XPWM channel signal is
driven directly or inverted to the port pin.
Clearing the enable bit PENx disconnects the XPWM channel and switches the respective
pin to the value in the port output latch XP.y.
Note:
To prevent further PWM pulses from occurring after such a software intervention the
respective counter must be stopped first.
Figure 27 shows the XPWM output signal generation.
XPWMPORT (EC80h)
XBus
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
XODP
.3
XP
.3
XDP
.3
XODP
.2
XP
.2
XDP
.2
XODP8
.1
XP
.1
XDP
.1
XODP
.0
XP
.0
XDP
.0
-RW
RW RW
RW
RW RW
RW
RW RW
RW
RW
RW
Table 60.
XPWMPORT register description
Bit
Bit name
Function
15-12
-
Reserved
11, 8, 5, 2
XODP.y
Port open-drain control register bit y
0: Port line XPOUT.y output driver in push-pull mode
1: Port line XPOUT.y output driver in open-drain mode
10, 7, 4, 1
XP.y
Port data register bit y
9, 6, 3, 0
XDP.y
Port direction register bit y
0: Port line XPOUT.y is an input (high impedance)
1: Port line XPOUT.y is an output
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