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ST10F296 数据表(PDF) 126 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 126 Page - STMicroelectronics |
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126 / 346 page  Obsolete Product(s) - Obsolete Product(s) Parallel ports ST10F296E 126/346 All port lines that are not used for alternate functions may be used as general purpose I/O lines. When using port pins for general purpose output, the initial output value should be written to the port latch prior to enabling the output drivers to avoid undesired transitions on the output pins. This applies to single pins as well as to pin groups (see example below). SINGLE_BIT: BSET P4.7 ; Initial output level is "high" BSET DP4.7 ; Switch on the output driver BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high" BFLDH DP4, #24H, #24H ; Switch on the output drivers Note: When using several BSET pairs to control several pins of one port, the pairs must be separated by instructions which do not apply to the respective port (see Section 7: Central processing unit (CPU) on page 92). 13.2 Port 0 The two 8-bit ports, P0H and P0L, represent the higher and lower part of Port 0, respectively. Both halves of Port 0 can be written (for example via a PEC transfer) without affecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers, DP0H and DP0L. 13.2.1 Port 0 registers P0L and P0H registers P0L (FF00h/80h) SFR Reset value: --00h 15 14 13 12 11 10 987 65432 10 Reserved P0L .7 P0L .6 P0L .5 P0L .4 P0L .3 P0L .2 P0L .1 P0L .0 - RW RW RW RW RW RW RW RW P0H (FF02h/81h) SFR Reset value: --00h 15 14 13 12 11 10 987 65432 10 Reserved P0H .7 P0H .6 P0H .5 P0H .4 P0H .3 P0H .2 P0H .1 P0H .0 - RW RW RW RW RW RW RW RW Table 67. P0L and P0H register description Bit Bit name Function 15-8 - Reserved 7-0 P0X.y Port data register P0L or P0H bit y Obsolete Product(s) - Obsolete Product(s) |
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