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ST10F296 数据表(PDF) 127 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 127 Page - STMicroelectronics |
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127 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Parallel ports 127/346 DP0L and DP0H registers 13.2.2 Alternate functions of Port 0 When an external bus is enabled, Port 0 is used as a data bus or an address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode is enabled). Port 0 is also used to select the system startup configuration. During reset, Port 0 is configured to input, and each line is held high through an internal pull-up device. Each line can now be individually pulled to a low level (see Section 24.5: DC characteristics) through an external pull-down device. A default configuration is selected when the respective Port 0 lines are at a high level. Through pulling individual lines to a low level, this default can be changed according to the needs of the applications. Internal pull-up devices are designed so that external pull-down resistors (see Section 24.5: DC characteristics) can be used to apply a correct low level. Such external pull-down resistors can remain connected to Port 0 pins during normal operation. However, care has to be taken that they do not disturb the normal function of Port 0 (for example, if the external resistor is too strong). At the end of reset, the selected bus configuration is written to the BUSCON0 register. The configuration of the high byte of Port 0, is copied into the RP0H register. RPOH is a read-only register that holds the selection for the number of chip selects and segment addresses. Software can read this register if required. When the reset is terminated, the internal pull-up devices are switched off, and Port 0 is switched to the appropriate operating mode. DP0L (F100h/80h) ESFR Reset value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DP0L .7 DP0L .6 DP0L .5 DP0L .4 DP0L .3 DP0L .2 DP0L .1 DP0L .0 - RW RW RW RW RW RW RW RW DP0H (F102h/81h) ESFR Reset value: --00h 15 14 13 12 11 10 9 8 7 6543 210 Reserved DP0H .7 DP0H .6 DP0H .5 DP0H .4 DP0H .3 DP0H .2 DP0H .1 DP0H .0 - RW RW RW RW RW RW RW RW Table 68. DP0L and DP0H register description Bit Bit name Function 15-8 - Reserved 7-0 DP0X.y Port direction register DP0L or DP0H bit y 0: Port line P0X.y is an input (high impedance) 1: Port line P0X.y is an output Obsolete Product(s) - Obsolete Product(s) |
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