ST10F296 datasheet(132/346 Pages) STMICROELECTRONICS

132 / 346 page

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Product(s)

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Parallel ports

ST10F296E

132/346

Figure 34.

Port 1 I/O and alternate functions

When an external bus mode is enabled, the direction of the port pin and the loading of data

into the port output latch are controlled by the bus controller hardware. The input of the port

output latch is disconnected from the internal bus and is switched to the line labeled

‘alternate data output’ via a multiplexer. The alternate data is the 16-bit intra-segment

address.

While an external bus mode is enabled, the user software should not write to the port output

latch, otherwise unpredictable results may occur. When the external bus modes are

disabled, the contents of the direction register that was last written by the user becomes

active.

Figure 35 shows the structure of a Port 1 pin.

Figure 35.

Block diagram of a Port 1 pin

PORT1

P1H

P1L

Alternate functions

(a)

General purpose

input/output

8/16-bit

demultiplexed bus

(b)

CAPCOM2

capture inputs

P1L.7

P1L.6

P1L.5

P1L.4

P1L.3

P1L.2

P1L.1

P1L.0

P1H.7

P1H.6

P1H.5

P1H.4

P1H.3

P1H.2

P1H.1

P1H.0

A15

A14

A13

A12

A11

A10

CC27I

CC26I

CC25I

CC24I

Direction

latch

Write DP1H.y/DP1L.y

Read DP1H.y / DP1L.y

Port output

latch

Write P1H.y/P1L.y

Read P1H.y/P1L.y

MUX

Input

latch

Clock

P1H.y

P1L.y

Output

buffer

y = 7 to 0

Alternate

function

enable

Port data

output

Alternate

data

output

Obsolete

Product(s)

- Obsolete

Product(s)

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