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ST10F296 数据表(PDF) 339 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 339 Page - STMicroelectronics |
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339 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Electrical characteristics 339/346 Figure 119. SSC master timing 1. The phase and polarity of the shift and latch edges of SCLK are programmable. Figure 119 uses the leading clock edge as the shift edge with the latch on the trailing edge (SSCPH = 0b). The idle clock line is low and the leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits that have to be transmitted or received. 1st out bit Last out bit 2nd out bit 2nd in bit 1st in bit SCLK MTSR MRST t308 t307 t308 t307 t305 t305 t306 t305 t304 t303 t300 t301 t302 Last in bit (1) (2) Obsolete Product(s) - Obsolete Product(s) |
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