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LSM6DSV 数据表(PDF) 101 Page - STMicroelectronics |
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LSM6DSV 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 187 page  9.72 UI_INT_OIS (6Fh) OIS interrupt configuration register The primary interface can write to this register when the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h) register is equal to 1 (primary IF full control mode); this register is read-only when the OIS_CTRL_FROM_UI bit is equal to 0 (SPI2 full control mode) and shows the content of the SPI2_INT_OIS (6Fh) register. Table 187. UI_INT_OIS register INT2_ DRDY_OIS DRDY_ MASK_OIS 0(1) ST_OIS_ CLAMPDIS 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to 0 for the correct operation of the device. Table 188. UI_INT_OIS register description INT2_DRDY_OIS Enables OIS chain DRDY on INT2 pin from the UI interface. This setting has priority over all other INT2 settings. DRDY_MASK_OIS Enables / masks OIS data available. Default value: 0 (0: disabled; 1: masks OIS DRDY on pin (both accelerometer and gyroscope) until filter settling ends (accelerometer and gyroscope independently masked)) ST_OIS_CLAMPDIS Disables OIS chain clamp during self-test. Default value: 0 (0: All OIS chain outputs = 8000h during self-test; 1: OIS chain self-test outputs) LSM6DSV UI_INT_OIS (6Fh) DS13476 - Rev 2 page 101/187 |
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