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ADP1050

Data Sheet

CS3 Overcurrent Protection

CS3 overcurrent protection provides alternative output overcurrent

protection if the direct output current sense is not available. The

reading is calculated from the CS1 and duty cycle readings.

The CS3_OC_FAULT flag (Register 0xFEA0[3]) is set when

the CS3 current reading of the eight most significant bits (MSBs)

in Register 0xFEA9 exceeds the CS3_OC_FAULT_LIMIT that is

programmed in Register 0xFE6A. The debounce time of the flag

setting can be programmed at 0 ms, 10 ms, 20 ms, or 200 ms in

is programmed in the CS3_OC_FAULT_RESPONSE bits

(Register 0xFE01[3:0]). See the Manufacturer Specific Protection

Responses section.

FLAGIN Protection

The SYNI/FLGI pin (Pin 10) can be configured in flag input mode

(FLGI). An external signal can be sent to the ADP1050 to trigger

an action. The polarity of the external signal is configured by the

FLGI polarity bit (Register 0xFE12[2]). When the ADP1050

detects an external signal, the FLAGIN flag is set. The response to

the FLAGIN flag is programmed in the FLAGIN_RESPONSE

bits (Register 0xFE03[3:0]). See the Manufacturer Specific

Protection Responses section.

VDD OVLO Protection

The ADP1050 has built-in overvoltage protection (OVP) on

its supply rail. The VDD overvoltage response bits (VDD_OV_

RESPONSE), found in Register 0xFE05[5:4], are used to specify

the response to a VDD overvoltage condition.

•

If Register 0xFE05[5] = 0, the VDD_OV flag is set and the

ADP1050 shuts down when the VDD voltage rises above the

OVLO threshold. When the VDD overvoltage condition ends,

the VDD_OV flag is cleared and the ADP1050 downloads

the EEPROM contents before restarting with a soft start

process. The debounce time of the VDD_OV flag can be

programmed using Register 0xFE05[4].

•

If Register 0xFE05[5] = 1, the VDD_OV flag is always

cleared, regardless of VDD voltage conditions. The

ADP1050 continues to operate without interruption.

It is recommended that the VDD_OV flag response not be

programmed as always cleared.

MANUFACTURER SPECIFIC PROTECTION

RESPONSES

For the VDD_OV flag and protection action, see the VDD

OVLO Protection section.

The following flags can be configured to trigger protection

responses: IIN_OC_FAST_FAULT, VOUT_OV_FAULT,

CS3_OC_FAULT, VIN_UV_FAULT, and FLAGIN. The

VOUT_OV_FAULT flag, which triggers the manufacturer

specific protection in Register 0xFE01[7:4], is used only for

conditional overvoltage protection. See the VOUT Overvoltage

Protection (OVP) section for details.

Each of the aforementioned flags can be individually programmed

to trigger one of the following responses:

•

Continue operation without interruption (flag ignored)

•

Disable SR1 and SR2

•

Disable all PWM outputs

After the condition that triggered the flag is resolved and the flag is

cleared, the ADP1050 can be programmed to respond as follows:

•

After the flag reenable delay time elapses, reenable the

disabled PWM outputs with a soft start sequence.

•

Reenable the disabled PWM outputs immediately without

the soft start process.

•

Keep the PWM output disabled. A PSON reset signal must

be used to reenable the PWM outputs with a soft start

sequence.

The first flag that causes all PWM outputs to be disabled and

requires a soft start if the PWM outputs are reenabled is

recorded as the first flag ID. For more information about use

of the first flag ID, see the First Flag ID Recording section.

A flag reenable delay can be set for the listed manufacturer

specific flags. This delay is used if the configured action for

a flag is to reenable the PWM outputs after the flag reenable delay.

This delay can be set to 250 ms, 500 ms, 1 sec, or 2 sec, using

Rev. A | Page 34 of 92

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