ADP1050ACPZ-R7 datasheet(77/93 Pages) AD

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ADP1050

Data Sheet

Table 111. Register 0xFE13—Dual-Ended Topology Mode

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

Dual-ended

topology enable

R/W

Setting this bit to 1 means that dual-ended topologies are used. It affects the modulation high limit.

The modulation limit in each half cycle is half of the modulation limit that is programmed in

0 = operates in single-ended topologies, such as buck, forward, and flyback.

1 = operates in dual-ended topologies, such as full bridge, half bridge, and push pull.

[5:0]

Reserved

R/W

Reserved.

CURRENT SENSE AND LIMIT SETTING REGISTERS

Table 112. Register 0xFE14—CS1 Gain Trim

Bits

Bit Name/Function

R/W

Description

Gain polarity

R/W

Setting this bit to 1 means that negative gain is introduced.

0 = positive gain is introduced.

1 = negative gain is introduced.

[6:0]

CS1 gain trim

R/W

This value calibrates the CS1 current sense gain. Apply 1 V dc at the CS1 pin. This register is

trimmed until the CS1 value reads 2560 decimal (0xA00).

Table 113. Register 0xFE19—CS3 OC Debounce

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

[6:5]

CS3_OC_FAULT flag

debounce

R/W

These two bits set the CS3_OC_FAULT flag debounce time.

Bit 6

Bit 5

Debounce Time (ms)

200

[4:0]

Reserved

R/W

Reserved.

Table 114. Register 0xFE1A—IIN_OC_FAST_FAULT_LIMIT

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

[6:4]

IIN_OC_FAST_

FAULT_LIMIT

R/W

If the CS1 cycle-by-cycle current-limit comparator is set and the CS1_OCP flag is triggered, all PWM

outputs that are on at that time can be programmed to be immediately disabled for the remainder

of the switching cycle. The PWM outputs resume normal operation at the beginning of the next

switching cycle.

There is an internal counter, N, with an initial value of 0. N counts the CS1_OCP flag triggering

number in consecutive switching cycles. If the CS1_OCP flag is triggered in one cycle, then NCURRENT =

NPREVIOUS + 2. If the CS1_OCP flag is not triggered in one cycle and the previous N > 0, then NCURRENT =

NPREVIOUS − 1. If the CS1_OCP flag is not triggered and the previous N = 0, then NCURRENT = 0. When N

reaches the IIN_OC_FAST_FAULT_LIMIT value, the IIN_OC_FAST_FAULT flag is set.

Note that there is one cycle in single-ended topologies, such as buck converter and forward

converter. There are two cycles in double-ended topologies, such as full bridge converter, half bridge

converter, and push pull converter.

Bit 6

Bit 5

Bit 4

Limit Value

128

256

512

1024

[3:0]

Reserved

R/W

Reserved.

Rev. A | Page 76 of 92

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