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Data Sheet

ADP1050

Voltage Sense ADCs

Two kinds of Σ-Δ ADCs are used in the ADP1050 feedback loop,

as follows:

•

Low frequency (LF) ADC, running at 1.56 MHz

•

High frequency (HF) ADC, running at 25 MHz

The Σ-Δ ADCs have a resolution of one bit and operate differently

from traditional flash ADCs. The equivalent resolution that is

obtained depends on how long the output bit stream of the Σ-Δ

ADC is filtered.

The Σ-Δ ADCs also differ from Nyquist rate ADCs in that the

quantization noise is not uniform across the frequency spectrum.

At lower frequencies, the noise decreases. At higher frequencies,

the noise increases (see Figure 19).

FREQUENCY

NYQUIST ADC

NOISE

Σ-Δ ADC

NOISE

Figure 19. ADC Noise Performance

The low frequency ADC runs at approximately 1.56 MHz. For

a specified bandwidth, the equivalent resolution is calculated as

ln(1.56 MHz/BW)/ln(2) = N bits

For example, at a bandwidth of 95 Hz, the equivalent resolution/

noise is

ln(1.56 MHz/95 Hz)/ln(2) = 14 bits

At a bandwidth of 1.5 kHz, the equivalent resolution/noise is

ln(1.56 MHz/1.5 kHz)/ln(2) = 10 bits

The high frequency ADC has a 25 MHz clock. It is comb filtered and

outputs at the switching frequency into the digital compensator. See

Table 5 for equivalent resolutions at selected sampling frequencies.

Table 5. Equivalent Resolutions for High Frequency ADC at

Selected Switching Frequencies

fSW (kHz)

High Frequency ADC Resolution (Bits)

49 to 87

97.5 to 184

195.5 to 379

390.5 to 625

The high frequency ADC has a range of ±25 mV. Using a base

switching frequency of 97.5 kHz at an 8-bit HF ADC resolution,

the quantization noise is 0.195 mV (1 LSB = 2 × 25 mV/28 =

0.195 mV). When the switching frequency increases to 195.5 kHz

at a 7-bit HF ADC resolution, the quantization noise is 0.391 mV

(1 LSB = 2 × 25 mV/27 = 0.391 mV). Increasing the switching

frequency to 390.5 kHz increases the quantization noise to 0.781 mV

(1 LSB = 2 × 25 mV/26 = 0.781 mV).

Output Voltage Adjustment Commands

In the ADP1050, the voltage data for commanding or reading

the output voltage or related parameters is in linear data format.

The linear format exponent is fixed at −10 decimal (see the

VOUT_MODE command, Register 0x20, in Table 21).

The following three basic commands are used for setting the

output voltage:

•

VOUT_COMMAND command (Register 0x21, Table 22)

•

VOUT_MARGIN_HIGH command (Register 0x25, Table 26)

•

VOUT_MARGIN_LOW command (Register 0x26, Table 27)

One of these three values is selected by the OPERATION command

(Register 0x01, Table 13).

The VOUT_MAX command (Register 0x24, Table 25) sets an

upper limit on the output voltage that the ADP1050 can command,

regardless of any other commands or combinations.

During output voltage adjustment, use the VOUT_TRANSITION_

RATE command (Register 0x27, Table 28) to set the rate (in mV/µs)

at which the VS± pins change voltage.

DIGITAL COMPENSATOR

Use the internal programmable digital compensator to change the

control loop of the power supply. A Type III digital compensator

architecture has been implemented. This Type III compensator is

reconstructed by a low frequency filter, with input from the low

frequency ADC, and a high frequency filter, with input from the

high frequency ADC. From the voltage sense ADC outputs to the

digital compensator output, the transfer function of the digital

compensator in z-domain is as follows:

( )

−

204

where:

a = HF filter pole register value/256 (Register 0xFE32/256).

b = HF filter zero registers value/256 (Register 0xFE31/256).

c = HF filter gain register value (Register 0xFE33).

d = LF filter gain register value (Register 0xFE30).

m is the scale factor, as follows:

m = 1 when 49 kHz ≤ fSW < 97.5 kHz

m = 2 when 97.5 kHz ≤ fSW < 195.5 kHz

m = 4 when 195.5 kHz ≤ fSW < 390.5 kHz

m = 8 when 390.5 kHz ≤ fSW

To tailor the loop response to the specific application, the low

frequency gain (represented by d), the zero location of the HF

filter (represented by b), the pole location of the HF filter

(represented by a), and the high frequency gain (represented by c)

can all be set up individually (see the Digital Compensator and

Modulation Setting Registers section).

Rev. A | Page 17 of 92

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