ADP1050ACPZ-R7 datasheet(86/93 Pages) AD

86 / 93 page

Data Sheet

ADP1050

VOLT-SECOND BALANCE CONTROL REGISTERS

Table 145. Register 0xFE54—Volt-Second Balance Control General Settings

Bits

Bit Name/Function

R/W

Description

Volt-second balance enable control

R/W

Setting this bit enables volt-second balance control.

[6:5]

Reserved

R/W

Reserved.

Volt-second balance control

source selection, OUTB

R/W

If this bit is set, OUTB rising edge is selected as the start of the integration period for

volt-second balance control.

Volt-second balance control

source selection, OUTA

R/W

If this bit is set, OUTA rising edge is selected as the start of the integration period for

volt-second balance control.

Volt-second balance control limit

R/W

This bit sets the maximum amount of modulation from the volt-second control circuit.

0 = ±160 ns.

1 = ±80 ns.

[1:0]

Volt-second balance control gain

R/W

These bits set the gain of the volt-second balance control. The gain can be changed by

a factor of 64. When these bits are set to 00, it takes approximately 700 ms to achieve

volt-second balance. When these bits are set to 11, it takes approximately 10 ms to

achieve volt-second balance.

Bit 1

Bit 0

Volt-Second Balance Loop Gain

Table 146. Register 0xFE55—Volt-Second Balance Control on OUTA and OUTB

Bits

Bit Name/Function

R/W

Description

tR2 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTB rising edge, tR2.

tR2 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR2 right.

1 = negative sign. Increase of balancing control modulation moves tR2 left.

tF2 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTB falling edge, tF2.

tF2 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF2 right.

1 = negative sign. Increase of balancing control modulation moves tF2 left.

tR1 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTA rising edge, tR1.

tR1 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR1 right.

1 = negative sign. Increase of balancing control modulation moves tR1 left.

tF1 balance setting

R/W

Setting this bit enables modulation from balancing control on the OUTA falling edge, tF1.

tF1 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF1 right.

1 = negative sign. Increase of balancing control modulation moves tF1 left.

Table 147. Register 0xFE57—Volt-Second Balance Control on SR1 and SR2

Bits

Bit Name/Function

R/W

Description

tR6 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR2 rising edge, tR6.

tR6 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR6 right.

1 = negative sign. Increase of balancing control modulation moves tR6 left.

tF6 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR2 falling edge, tF6.

tF6 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF6 right.

1 = negative sign. Increase of balancing control modulation moves tF6 left.

tR5 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR1 rising edge, tR5.

tR5 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tR5 right.

1 = negative sign. Increase of balancing control modulation moves tR5 left.

tF5 balance setting

R/W

Setting this bit enables modulation from balancing control on the SR1 falling edge, tF5.

tF5 balance direction

R/W

0 = positive sign. Increase of balancing control modulation moves tF5 right.

1 = negative sign. Increase of balancing control modulation moves tF5 left.

Rev. A | Page 85 of 92

ADP1050ACPZ-R7 数据表(PDF) 86 Page - Analog Devices

ADP1050ACPZ-R7 数据表(HTML) 86 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表下载

链接网址

ADP1050ACPZ-R7 数据表(PDF) 86 Page - Analog Devices

ADP1050ACPZ-R7 数据表(HTML) 86 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表 下载

链接网址

数据表下载