ADP1050ACPZ-R7 datasheet(80/93 Pages) AD

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Data Sheet

ADP1050

Table 122. Register 0xFE28—VF Gain Trim

Bits

Bit Name/Function

R/W

Description

Trim polarity

R/W

0 = positive gain is introduced.

1 = negative gain is introduced.

[6:0]

VF trim

R/W

These bits set the amount of gain trim that is applied to the VF ADC reading. This register trims the

voltage at the VF pin for external resistor tolerances. When there is 1 V on the VF pin, this register is

trimmed until the VF value register reads 1280 decimal (0x500).

Table 123. Register 0xFE29—VIN_ON and VIN_OFF Delay

Bits

Bit Name/Function

R/W

Description

[7:6]

Reserved

R/W

Reserved

VIN_UV_FAULT enable

R/W

Setting this bit enables the VIN_ON value and the VIN_OFF value used to generate the VIN_UV_FAULT flag.

Power conversion

stop delay

R/W

Sets the delay time from when the VIN_LOW flag is set to when the power conversion stops.

0 = 0 ms.

1 = 1 ms.

[3:2]

Power conversion

start delay

R/W

Sets the delay time from the clearing of the VIN_LOW flag to the start of the power conversion.

Bit 3

Bit 2

Delay Time (ms)

[1:0]

VIN_UV_FAULT flag

debounce

R/W

When Bit 5 is set, sets the VIN_UV_FAULT flag debounce time.

Bit 1

Bit 0

Typical Debounce Time (ms)

2.5

100

TEMPERATURE SENSE AND PROTECTION SETTING REGISTERS

Table 124. Register 0xFE2A—RTD Gain Trim

Bits

Bit Name/Function

R/W

Description

Gain polarity

R/W

Setting this bit to 1 means that negative gain is introduced. Setting this bit to 0 means that

positive gain is introduced.

[6:0]

RTD gain trim

R/W

This value calibrates the RTD sensing gain.

Table 125. Register 0xFE2B—RTD Offset Trim (MSBs)

Bits

Bit Name/Function

R/W

Description

[7:3]

Reserved

R/W

Reserved.

RTD current source

disable

R/W

Setting this bit to 1 and writing 0x00 to Register 0xFE2D disables the RTD current source.

Trim polarity

R/W

Setting this bit to 1 means that negative offset is introduced. Setting this bit to 0 means that

positive offset is introduced.

RTD offset trim, MSB

R/W

This bit, together with Register 0xFE2C as the LSBs, sets the amount of offset trim that is applied to

the RTD ADC reading.

Table 126. Register 0xFE2C—RTD Offset Trim (LSBs)

Bits

Bit Name/Function

R/W

Description

[7:0]

RTD offset trim, LSBs

R/W

These eight bits, together with Bit 0 in Register 0xFE2B as the MSB, set the amount of offset trim

that is applied to the RTD ADC reading.

Rev. A | Page 79 of 92

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