ADP1050ACPZ-R7 datasheet(15/93 Pages) AD

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ADP1050

Data Sheet

The advantage of the SR soft start is that it minimizes the output

voltage undershoot that occurs when the SR FETs are turned on

without a soft start. The advantage of turning the SRx signals

completely on immediately is that they can help minimize the

voltage transient caused during a load step.

Using Register 0xFE08[4], the SR soft start can be programmed to

occur only once (the first time that the SRx signals are enabled) or

every time that the SRx signals are enabled.

When programming the ADP1050 to use the SR soft start, ensure

the correct operation of this function by setting the falling edge of

SR1 (tF5) to a lower value than the rising edge of SR1 (tR5) and setting

the falling edge of SR2 (tF6) to a lower value than the rising edge of

SR2 (tR6). During the SR soft start, the rising edges of SRx move

gradually from the right side (the tRX + tMODU_LIMIT position) to the

left side to increase the duty cycle.

The ADP1050 is well suited for dc-to-dc converters in isolated

topologies. Every time a PWM signal crosses the isolation barrier,

a propagation delay is added because of the isolating components.

Using Register 0xFE3A[5:0], an adjustable delay (0 ns to 315 ns in

steps of 5 ns) can be programmed to move both SR1 and SR2 later

in time to compensate for the added propagation delay. In this way,

all the PWM edges can be aligned (see Figure 58).

PWM MODULATION LIMIT AND 180° PHASE SHIFT

The modulation limit register (Register 0xFE3C) can be programmed

to apply a maximum modulation limit to any PWM signal, thus

limiting the modulation range of any PWM output. If modulation

is enabled, the maximum modulation limit is applied to all PWM

outputs collectively. This limit, tMODU_LIMIT, is the maximum time

variation for the modulated edges from the default timing, following

the configured modulation direction (see Figure 13). There is no

setting for the minimum duty cycle limit. Therefore, the user must

set the rising edges and falling edges based on the case with the least

modulation.

tRX

tFX

tRY

tFY

OUTX

OUTY

tMODU_LIMIT

tS/2

tMODU_LIMIT

Figure 13. Setting Modulation Limits

Each least significant bit (LSB) in Register 0xFE3C corresponds to

a different time step size, depending on the switching frequency

(see Table 137). If the ADP1050 is to control a dual-ended topology

(such as full bridge, half bridge, or push pull), enable the dual-ended

topology mode using Register 0xFE13[6]. When dual-ended

topology mode is enabled, the modulation limit in each half cycle

is half of the modulation value programmed by Register 0xFE3C.

The modulated edges cannot go beyond one switching cycle. To

extend the modulation range for some applications, the 180°

phase shift can be enabled, using Register 0xFE3B[5:4] and

rising edge timing and the falling edge timing are referred to the

start of the switching cycle (see tRX and tFX in Figure 13). When the

180° phase shift is enabled, the rising edge timing and the falling

edge timing are referred to half of the switching cycle (see tRY and

tFY in Figure 13, which are referred to tS/2). Therefore, when the

180° phase shift is disabled, the edges are always located between t0

and tS. When the 180° phase shift is enabled, the edges are located

between tS/2 and 3tS/2.

The 180° phase shift function can be used to extend the maximum

duty cycle in a multiphase, interleaved converter. Figure 14 shows

a dual phase, interleaved buck converter. The OUTB and SR1

PWM outputs can be programmed with a 180° phase shift with the

OUTA and SR2 PWM outputs.

The ADP1050 GUI is recommended for evaluating this feature.

LOAD

INPUT

DRIVER

Figure 14. Dual Phase, Interleaved Buck Converter Controlled by the ADP1050

FREQUENCY SYNCHRONIZATION

The ADP1050 can be programmed as a slave device to use the

SYNI/FLGI pin signal as the reference to synchronize the internal

programmed PWM clock with an external clock.

The period of the external clock that is applied at the SYNI/FLGI pin

must be in the range of 90% to 110% of the period of the internal

programmed PWM clock. The minimum pulse width of the SYNI

signal is 360 ns. From the rising edge of the SYNI signal to the start

of the internal clock cycle, there is a 760 ns propagation delay. To

realize interleaving control with different controllers, additional

delay time can be programmed using Register 0xFE11.

To achieve a smooth synchronization transition between asynchro-

nous operation and synchronous operation, there is a phase capture

range bit for synchronization in Register 0xFE12[6] for capturing

the phase of the external clock signal. The ADP1050 detects the

phase shift between the external clock signal and the internal clock

signal when synchronization is enabled. When the phase shift falls

within the phase capture range, synchronization begins.

Rev. A | Page 14 of 92

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