ADP1050ACPZ-R7 datasheet(89/93 Pages) AD

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ADP1050

Data Sheet

Table 159. Register 0xFE6C—Modulation Flag for OVP Selection

Bits

Bit Name/Function

R/W

Description

[7:3]

Reserved

R/W

Reserved.

LARGE_MODULATION

This bit is set when the modulation value is above the threshold set in Register 0xFE6B.

VIN feedforward

prebias startup

R/W

This bit is applicable only if the closed-loop feedforward operation is disabled (Register 0xFE3D[2] = 0).

If the closed-loop feedforward operation is enabled, VIN is always included for the calculation of

the initial PWM modulation value.

1 = the initial PWM modulation value is calculated by the nominal modulation value (Register 0xFE39),

the sensed VIN voltage, and the sensed VOUT voltage.

0 = the initial PWM modulation value is calculated by the nominal modulation value (Register 0xFE39)

and the sensed VOUT voltage. The VIN voltage is ignored.

Conditional OVP

enable

R/W

This bit sets the OVP actions when the VOUT_OV_FAULT flag is triggered.

0 = conditional OVP is disabled. The OVP action follows the PMBus VOUT_OV_FAULT_RESPONSE

command (Register 0x41).

1 = conditional OVP is enabled. If Bit 2 = 1, OVP action follows the PMBus VOUT_OV_FAULT_RESPONSE

(Register 0x41). If Bit 2 = 0, OVP action follows the extended VOUT_OV_FAULT_RESPONSE action

(Register 0xFE01[7:4]).

Table 160. Register 0xFE6D—OUTA and OUTB Adjustment Reference During Synchronization

Bits

Bit Name/Function

R/W

Description

tR2 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTB rising edge, tR2.

tR2 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF2 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTB falling edge, tF2.

tF2 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tR1 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTA rising edge, tR1.

tR1 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF1 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTA falling edge, tF1.

tF1 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

Table 161. Register 0xFE6F—SR1 and SR2 Adjustment Reference During Synchronization

Bits

Bit Name/Function

R/W

Description

tR6 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR2 rising edge, tR6.

tR6 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF6 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR2 falling edge, tF6.

tF6 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tR5 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR1 rising edge, tR5.

tR5 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF5 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR1 falling edge, tF5.

tF5 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

Rev. A | Page 88 of 92

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