ADP1050ACPZ-R7 datasheet(19/93 Pages) AD

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ADP1050

Data Sheet

It is recommended that the ADP1050 GUI be used to program the

compensator. The GUI displays the filter response, using a Bode

plot in the s-domain, and calculates all stability criteria for the

power supply.

To transfer the z-domain value to the s-domain, plug the following

bilinear transformation equation into the H(z) equation:

z(s)

−

where s is the s-domain value.

The filter introduces an extra phase delay element into the control

loop. The digital compensator circuit sends the information about

the duty cycle to the digital PWM engine at the beginning of each

switching cycle (unlike an analog controller, which makes decisions

on the duty cycle information continuously). There is an additional

delay for ADC sampling and decimation filtering. This extra phase

delay for phase margin (Φ) is expressed as follows:

Φ = 360 × fC/fSW

where

fC is the crossover frequency.

fSW is the switching frequency.

At one-tenth the switching frequency, the phase delay is 36°. The

GUI incorporates this phase delay into its calculations. Note that

the ADP1050 GUI does not account for other delays, such as gate

driver and propagation delay.

The main compensator, called the normal mode compensator, is

programmed using Register 0xFE30 to Register 0xFE33. In

addition, a dedicated filter is used during soft start. The filter

is disabled at the end of the soft start routine, after which the

voltage loop digital compensator is used. The soft start filter gain

is a programmable value of 1, 2, 4, or 8, using Register 0xFE3D[1:0].

CLOSED-LOOP INPUT VOLTAGE FEEDFORWARD

CONTROL AND VF SENSE

The ADP1050 supports closed-loop input voltage feedforward

control to improve input transient performance. The VF value is

sensed by the feedforward ADC and is used to divide the output

of the digital compensator. The result is fed into the digital PWM

engine. The input voltage signal can be sensed at the center tap in

the secondary windings of the isolation transformer and must be

filtered by a residual current device (RCD) circuit network to

eliminate the voltage spike at the switching node. Alternatively, the

input voltage signal can be sensed from a winding of the auxiliary

power transformer.

The VF pin (Pin 4) voltage must be set to 1 V when the nominal

input voltage is applied. The feedforward ADC sampling period is

10 μs. Therefore, the decision to modify the PWM outputs, based

on the input voltage, is performed at this rate.

As shown in Figure 20, the feedforward scheme modifies the

modulation value, based on the VF voltage. When the VF input

is 1 V, the line voltage feedforward has no effect. For example, if

the digital compensator output remains unchanged and the VF

voltage changes to 50% of its original value (still greater than 0.5 V),

the modulation of the OUTx edges that are configured for

modulation doubles.

DIGITAL

COMPENSATOR

DPWM

ENGINE

1/x

Σ-Δ

ADC

READ_VIN

REG 0x88

REG 0x35,

REG 0x36

FEED-

FORWARD

ADC

0.5V TO 1.6V

0V TO 1.6V

VIN_LOW

FLAG REG 0x7C[3]

REG 0xFE29[5]

VIN_UV_FAULT

FLAG REG 0x7C[4]

FROM THE VIN

SENSE CIRCUIT

Figure 20. Closed-Loop Input Voltage Feedforward Configuration

If the digital compensator output remains unchanged and the VF

voltage changes to 200% of its original value (still less than 1.6 V), the

modulation of the OUTx edges that are configured for modulation

is divided by 2 (see Figure 21). Register 0xFE3D[3:2] is used to

program the optional input voltage feedforward function.

The VF pin also has a low speed, high resolution Σ-Δ ADC. The

ADC has an update rate of 800 Hz with 11-bit resolution. The

ADC output value is stored in Register 0xFEAC and converted

to the READ_VIN command (Register 0x88). This value provides

information for the input voltage monitoring and flag functions.

DIGITAL

FILTER

OUTPUT

OUTx

tMODULATION

Figure 21. Closed-Loop Input Voltage Feedforward Changes Modulation

Values

Rev. A | Page 18 of 92

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