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ADP1050

Data Sheet

SYNI/FLGI

SYNI DELAY

TIME SETTING

REG 0xFE11

±3.125%

±6.25%

SYNC OPERATION

AS SLAVE DEVICE

0µs

DEBOUNCE

100µs

DEBOUNCE

FLAGIN FLAG

RESPONSE

REG 0xFE03[3:2]

SYNI MODE

FLGI MODE

SYNI ENABLE

REG 0xFE12[3]

DEBOUNCE TIME

REG 0xFE12[1]

POLARITY

REG 0xFE12[2]

PHASE CAPTURE

RANGE SELECTION

REG 0xFE12[6]

SYNI/FLGI

SELECTION

REG 0xFE12[0]

320ns

DEBOUNCE

Figure 16. Synchronization Configuration

Figure 17. Edge Adjustment Reference During Synchronization

To ensure a constant dead time before and after synchronization,

referred to tS/2 or tS. For example, the falling edge of OUTA (tF1) is

referred to the ½ × tS position, which means that the time difference

between tF1 and ½ × tS is a constant during the synchronization

transition. Figure 17 shows an example of the edge adjustment

reference settings in a full bridge topology.

OUTPUT VOLTAGE SENSE AND ADJUSTMENT

The output voltage sense and adjustment function is used for

control, monitoring, and undervoltage protection of the remote

output voltage. VS− (Pin 2) and VS+ (Pin 3) are fully differential

inputs. The voltage sense point can be calibrated digitally to remove

any errors due to external components. This calibration can be

performed in the production environment, and the settings can

be stored in the EEPROM of the ADP1050 (see the Power Supply

Calibration and Trim section for more information).

For voltage monitoring, the READ_VOUT output voltage command

(Register 0x8B) is updated every 10 ms. The ADP1050 stores every

ADC sample for 10 ms and then calculates the average value at the

end of the 10 ms period. Therefore, if Register 0x8B is read at least

every 10 ms, a true average value is obtained. The voltage information

is available through the I2C/PMBus interface.

The control loop of the ADP1050 features a patented multipath

architecture. The output voltage is converted simultaneously by two

ADCs: a high accuracy ADC and a high speed ADC. The complete

signal is reconstructed and processed in the digital compensator

to provide a high performance and cost competitive solution.

Voltage Feedback Sensing (VS+ and VS− Pins)

The voltage sense point on the power rail requires an external

resistor divider (R1 and R2 in Figure 18) to bring the nominal

differential mode signal to 1 V between the VS+ and VS− pins (see

Figure 18). This external resistor divider is necessary because the

VS ADC input range of the ADP1050 is 0 V to 1.6 V. When R1

and R2 are known, the VOUT_SCALE_LOOP parameter can be

calculated using the following equation:

VOUT_SCALE_LOOP = R2/(R1 + R2)

In a 12 V system with resistor dividers of 11 kΩ and 1 kΩ,

VOUT_SCALE_LOOP can be calculated as follows:

VOUT_SCALE_LOOP = 1 kΩ/(11 kΩ + 1 kΩ) = 0.08333

LOAD

DIGITAL

COMPENSATOR

VS+

VS–

VOLTAGE SENSE

REGISTERS

HIGH SPEED

ADC

VOUT_UV_FAULT FLAG

VOUT_UV_FAULT_LIMIT

ACCURATE

ADC

Figure 18. Voltage Sense Configuration

Rev. A | Page 16 of 92

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