ADP1050ACPZ-R7 datasheet(82/93 Pages) AD

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Data Sheet

ADP1050

Table 131. Register 0xFE32—Normal Mode Compensator Pole Settings

Bits

Bit Name/Function

R/W

Description

[7:0]

Normal mode

pole settings

R/W

This register determines the position of the pole of the digital compensator in normal mode.

See Figure 56.

Table 132. Register 0xFE33—Normal Mode Compensator High Frequency Gain Settings

Bits

Bit Name/Function

R/W

Description

[7:0]

Normal mode high

frequency gain

R/W

This register determines the high frequency gain of the digital compensator in normal mode. It is

programmable over a 48.13 dB range. See Figure 56.

Table 133. Register 0xFE38—CS1 Threshold for Volt-Second Balance

Bits

Bit Name/Function

R/W

Description

[7:0]

CS1 threshold for

volt-second balance

R/W

This register sets the CS1 threshold to enable volt-second balance control. The volt-second balance

control function is activated only if the CS1 value is greater than this threshold value. Each LSB is

6.25 mV.

Table 134. Register 0xFE39—Nominal Modulation Value for Prebias Startup

Bits

Bit Name/Function

R/W

Description

[7:0]

Nominal modulation

value for prebias

start-up function

R/W

These bits set the nominal modulation value when the input voltage and the output voltage are in

nominal conditions. It is used to calculate the initial modulation value, based on the sensed VOUT value

and the sensed VIN value, for the prebias startup. If Register 0xFE6C[1] is cleared, the input voltage is

always regarded as the nominal input condition unless closed-loop feedforward operation is in use.

Switching Frequency Range (kHz)

Resolution Corresponding to LSB (ns)

49 to 87

97.5 to 184

195.5 to 379

390.5 to 625

Table 135. Register 0xFE3A—SR Driver Delay

Bits

Bit Name/Function

R/W

Description

[7:6]

Reserved

R/W

Reserved.

[5:0]

SR gate drive delay

R/W

These bits set the SR gate drive delay in steps of 5 ns, from 0 ns to a maximum of 315 ns.

Table 136. Register 0xFE3B—PWM 180° Phase Shift Settings

Bits

Bit Name/Function

R/W

Description

Volt-second balance

leading edge blanking

R/W

Setting this bit means that CS1 is blanked for volt-second balance calculations at the rising edge of

those PWMs selected for volt-second balance. The blanking time is the same as for the CS1 cycle-

by-cycle current-limit setting.

Volt-second balance

50% blanking of each

phase

R/W

Setting this bit limits the sampling period for the current on CS1 to less than 50% of a half cycle.

SR2 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the SR2 edges.

SR1 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the SR1 edges.

[3:2]

Reserved

R/W

Reserved.

OUTB 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the OUTB edges.

OUTA 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the OUTA edges.

Rev. A | Page 81 of 92

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