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ADP1050ACPZ-R7 数据表(PDF) 10 Page - Analog Devices |
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ADP1050ACPZ-R7 数据表(HTML) 10 Page - Analog Devices |
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10 / 93 page  Data Sheet ADP1050 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 14 13 12 1 3 4 PG/ALT 15 VCORE CTRL SDA 11 SCL OVP VS+ 2 VS– VF 5 CS1 ADP1050 TOP VIEW (Not to Scale) NOTES 1. THE ADP1050 HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE OF THE PACKAGE. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE PCB AGND PLANE. Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 OVP Overvoltage Protection. This signal is used as redundant overvoltage protection. This signal is referred to AGND. 2 VS− Inverting Voltage Sense Input. This pin is the connection for the ground line of the power rail. Provide a low ohmic connection to AGND. To allow trimming, it is recommended that the resistor divider on this input have a tolerance specification of ≤0.5%. 3 VS+ Noninverting Voltage Sense Input. This signal is referred to VS−. To allow trimming, it is recommended that the resistor divider on this input have a tolerance specification of ≤0.5%. 4 VF Voltage Feedforward. Three optional functions can be implemented with this pin: feedforward, primary side input voltage sensing, and input voltage UVLO protection. The pin is connected upstream of the output inductor through a resistor divider network. The nominal voltage at this pin is 1 V. This signal is referred to AGND. 5 CS1 Primary Side Current Sense Input. This pin is connected to the primary side current sensing ADC and to the cycle- by-cycle current-limit comparator. This signal is referred to AGND. To allow trimming, it is recommended that the resistors on this input have a tolerance specification of ≤0.5%. If this pin is not used, connect it to AGND. 6 SR1 PWM Logic Output Drive. This pin can be disabled when not in use. This signal is referred to AGND. 7 SR2 PWM Logic Output Drive. This pin can be disabled when not in use. This signal is referred to AGND. 8 OUTA PWM Logic Output Drive. This pin can be disabled when not in use. This signal is referred to AGND. 9 OUTB PWM Logic Output Drive. This pin can be disabled when not in use. This signal is referred to AGND. 10 SYNI/FLGI Synchronization Signal Input (SYNI)/External Signal Input to Generate a Flag Condition (FLGI). If this pin is not used, connect it to AGND. 11 SCL I2C/PMBus Serial Clock Input and Output (Open Drain). This signal is referred to AGND. 12 SDA I2C/PMBus Serial Data Input and Output (Open Drain). This signal is referred to AGND. 13 CTRL PMBus Control Signal. It is recommended that a 1 nF capacitor be connected from the CTRL pin to AGND for noise debounce and decoupling. This signal is referred to AGND. 14 PG/ALT Power-Good Output (Open Drain)(PG)/Active Low SMBus ALERT Signal (ALT). Connect this pin to VDD using a pull- up resistor (typically 2.2 kΩ). The power-good signal is referred to AGND. For information about the SMBus specification, see the PMBus Features section. 15 VCORE Output of the 2.6 V Regulator. Connect a decoupling capacitor of at least 330 nF from this pin to AGND, as close as possible to the ADP1050 to minimize the PCB trace length. It is recommended that this pin not be used as a reference or to generate other logic levels using resistive dividers. 16 VDD Positive Supply Input. Voltage of 3.0 V to 3.6 V. This signal is referred to AGND. Connect a 2.2 μF decoupling capacitor from this pin to AGND, as close as possible to the ADP1050 to minimize the PCB trace length. 17 AGND Common Analog Ground. The internal analog circuitry ground and the digital circuitry ground are star connected to this pin through bonding wires. 18 RES Resistor Input. This pin sets the internal reference for the internal PLL frequency. Connect a 10 kΩ resistor (±0.1%) from this pin to AGND. This signal is referred to AGND. 19 ADD Address Select Input. This pin is used to program the I2C/PMBus address. Connect a resistor from ADD to AGND. This signal is referred to AGND. Rev. A | Page 9 of 92 |
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