ADP1050ACPZ-R7 datasheet(14/93 Pages) AD

14 / 93 page

Data Sheet

ADP1050

PWM OUTPUTS (OUTA, OUTB, SR1, AND SR2)

The PWM outputs are used for control of the primary side drivers

and the synchronous rectifier drivers. They can be used for several

topologies, including hard-switched full bridge, half bridge, push

pull, two-switch forward, active clamp forward, and interleaved

buck. Delays between rising and falling edges can be individually

programmed. Special care must be taken to avoid shootthrough and

cross conduction. It is recommended that the ADP1050 GUI

software be used to program these outputs.

Figure 11 shows an example configuration to drive an active clamp

forward topology with synchronous rectification. The QA, QB,

QSR1, and QSR2 switches are driven separately by the PWM outputs

(OUTA, OUTB, SR1, and SR2). Figure 12 shows an example of the

PWM settings in the GUI for the power stage shown in Figure 11.

The PWM outputs are all synchronized with each other. Therefore,

when reprogramming more than one of these outputs, it is

important to first update all of the registers and then latch the

information into the shadow registers at one time. During the

reprogramming operation, the outputs are temporarily disabled. To

ensure that the new PWM timings and the switching frequency

setting are programmed simultaneously, a special instruction is

sent to the ADP1050 by setting Register 0xFE61[2:1] (the go

commands). It is recommended that the PWM outputs not in use be

disabled via Register 0xFE53[5:4] and Register 0xFE53[1:0].

See the PWM Outputs Timing Registers section for additional

information about the PWM timings.

SYNCHRONOUS RECTIFICATION

SR1 and SR2 are recommended for use as the PWM control signals

when synchronous rectification is in use. These PWM signals can

be configured much like the other PWM outputs.

An optional soft start can be applied to the synchronous rectifier

(SR) PWM outputs. The SR soft start can be programmed using

•

When the SR soft start is disabled (Register 0xFE08[1:0] = 00),

the SR signals are immediately turned on to their modulated

PWM duty cycle values.

•

When the SR soft start is enabled (Register 0xFE08[1:0] =

11), the SR1 and SR2 rising edges move left from the tRX +

tMODU_LIMIT position to the tRX + tMODULATION position in steps

that are set in Register 0xFE08[3:2]. tRX represents the rising

edge timing of SR1 (tR5) and the rising edge timing of SR2

(tR6) (see Figure 58); tMODU_LIMIT represents the modulation

limit defined in Register 0xFE3C (see Figure 57); tMODULATION

represents the real-time modulation value.

•

The SR soft start is still applicable even if the SR1 and SR2

outputs are not programmed to be modulated. When the SR

soft start is enabled, the SR1 and SR2 rising edges move left

from the tRX + tMODU_LIMIT position to the tRX position in steps

that are set in Register 0xFE08[3:2].

OUTA

OUTB

SR1

SR2

INPUT

ISOLATED

DRIVER

QSR2

QSR1

Figure 11. PWM Assignment for Active Clamp Forward Topology with Synchronous Rectification

Figure 12. PWM Settings for Active Clamp Forward Topology with Synchronous Rectification Using the ADP1050 GUI

Rev. A | Page 13 of 92

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