ADP1050ACPZ-R7 datasheet(76/93 Pages) AD

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Data Sheet

ADP1050

Table 108. Register 0xFE0F—Debounce Time for Asserting PGOOD

Bits

Bit Name/Function

R/W

Debounce Time (ms)

VIN_UV_FAULT to assert PGOOD

R/W

0 = 0

1 = 1.3

IIN_OC_FAST_FAULT to assert PGOOD

R/W

0 = 0

1 = 1.3

Reserved

R/W

Reserved.

VOUT_OV_FAULT to assert PGOOD

R/W

0 = 0

1 = 1.3

VOUT_UV_FAULT to assert PGOOD

R/W

0 = 0

1 = 1.3

OT_FAULT to assert PGOOD

R/W

0 = 0

1 = 1.3

OT_WARNING to assert PGOOD

R/W

0 = 0

1 = 1.3

Reserved

R/W

Reserved.

SWITCHING FREQUENCY AND SYNCHRONIZATION REGISTERS

When synchronization is enabled, the ADP1050 takes the SYNI signal and adds the tSYNC_DELAY, together with a 760 ns propagation delay, to

generate the internal synchronization reference clock as shown in Figure 55. The ADP1050 uses the reference clock to generate its own clock.

760ns +

tSYNC_DELAY

CLOCKSYNC

SYNI

Figure 55. Synchronization Timing

Table 109. Register 0xFE11—Synchronization Delay Time

Bits

Bit Name/Function

R/W

Description

[7:0]

tSYNC_DELAY

R/W

Sets the additional delay of the synchronization reference clock to the rising edge of the SYNI signal.

Each LSB size is 40 ns.

Note that this delay time cannot exceed one switching period. If the PWM 180° phase shift is

enabled, this delay time cannot exceed half of one switching period.

Table 110. Register 0xFE12—Synchronization General Settings

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

Phase capture range

for synchronization

R/W

Sets the phase capture range. The ADP1050 detects the phase shift between the external and internal

clocks when synchronization is enabled. When the phase shift falls within the range, synchronization starts.

0 = phase capture range is ±3.125% (±11.25°).

1 = phase capture range is ±6.25% (±22.5°). This is the recommended setting.

[5:4]

Reserved

R/W

Reserved.

Enable

synchronization

R/W

This bit enables frequency synchronization as a slave device. The ADP1050 synchronizes with the external

clock through the SYNI/FLGI pin. Bit 0 = 0 if synchronization is enabled.

FLGI polarity

R/W

Sets the polarity for the SYNI/FLGI pin when the pin is programmed as FLGI.

0 = a high logic level on the SYNI/FLGI pin sets the FLAGIN flag; a low logic level clears the FLAGIN flag.

1 = a low logic level on the SYNI/FLGI pin sets the FLAGIN flag; a high logic level sets the FLAGIN flag.

FLAGIN flag

debounce time

R/W

0 = 0 μs debounce time for the FLAGIN flag.

1 = 100 μs debounce time for the FLAGIN flag.

SYNI/FLGI

pin function

selection

R/W

Configures the SYNI/FLGI pin as a flag input or a synchronization input. When SYNI is not enabled,

this bit must be set to 1.

0 = the SYNI/FLGI pin is used as the synchronization input (SYNI).

1 = the SYNI/FLGI pin is used as the flag input (FLGI).

Rev. A | Page 75 of 92

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