ADP1050ACPZ-R7 datasheet(24/93 Pages) AD

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Data Sheet

ADP1050

PULSE SKIPPING

The pulse skipping function can reduce the switching loss under

very light load current conditions while keeping the output voltage

stable. Register 0xFE67[6] can be set to activate this function.

As the output current falls, the supply enters discontinuous

conduction mode (DCM). In DCM, the modulation value is a

function of the load current. If a very light load current requires

a modulation value (duty cycle) of less than the threshold set by

mode, the PWM output appears intermittently. If the digital

compensator signals an error requiring a modulation value that is

less than the threshold set by Register 0xFE69, no PWM pulses are

generated. If the digital compensator signals an error requiring a

modulation value that is greater than the threshold that is set by

mode is always blanked during soft start.

PREBIAS STARTUP

The prebias start-up function provides the capability to start up

the ADP1050 with a prebiased voltage on the output. It protects

the power supply against existing external voltage on the output

during startup and ensures a monotonic startup before the power

supply reaches full regulation (see Figure 27).

VOUT

PSON

PWM

OUTPUTS

Figure 27. Prebias Startup

The prebias start-up function is enabled by Register 0xFE25[7].

During prebias startup, the ADP1050 soft start ramp starts at

the existing voltage value sensed on the VS± pins, and the soft

start ramp time is reduced proportionally. The initial PWM

modulation value does not begin with zero but, instead, with

a value that builds a balanced relationship between the input

voltage and the output voltage. This balance avoids the sudden

charging or discharging of the output capacitor and achieves

a monotonic and smooth startup. The initial modulation value

is calculated by the following equation:

NOM

OUT

NOM

MODU

INI

MODU

where:

tMODU_INI is the initial modulation value when the controller begins

to generate PWM pulses during startup.

tMODU_NOM is the modulation value set by Register 0xFE39. This

value emulates the modulation value when the input voltage

and the output voltage are in the nominal condition.

VOUT is the output voltage sensed on the VS± pins.

VOUT_NOM is the nominal output voltage set by VOUT_COMMAND

(Register 0x21).

VIN_NOM is the nominal input voltage when the VF pin voltage = 1 V.

VIN is the sensed input voltage.

In addition, Register 0xFE6C[1] is set for correct operation. To

sense the input voltage (represented by VF) when the power supply

is off, use additional circuitry, such as an auxiliary power circuit,

to sense the input voltage.

If the input voltage signal is not available when the power is off,

the tMODU_INI value is calculated based on the tMODU_NOM and the

output voltage information. In this case, Register 0xFE6C[1]

is cleared to 0.

The initial modulation value is calculated as follows:

NOM

OUT

NOM

MODU

INI

MODU

where:

tMODU_INI is the initial modulation value when the controller begins

to generate PWM pulses during startup.

tMODU_NOM is the modulation value set by Register 0xFE39. This

value emulates the modulation value when the input voltage

and the output voltage are in the nominal condition.

VOUT is the output voltage sensed on the VS± pins.

VOUT_NOM is the nominal output voltage set by VOUT_COMMAND

(Register 0x21).

If the closed-loop line voltage feedforward function is selected,

the input voltage is introduced from the feedforward loop, and

the VIN value is always included for calculation of the initial

modulation value.

SR soft start can also be enabled in this mode to achieve a smooth

transition. See the Synchronous Rectification section for more

information.

VDD AND VCORE

When the voltage of the VDD pin (VDD) is applied, there is a

delay before the ADP1050 can regulate the power supply. When

VDD rises above the power-on reset and UVLO levels, it takes

~20 μs for the VCORE pin (Pin 15) to reach its operational point

of 2.6 V. The EEPROM contents are then downloaded to the

registers. The download takes approximately 120 μs. After the

EEPROM contents are downloaded, the ADP1050 is ready for

operation; however, it takes a maximum of 52 ms for the ADP1050

to complete initialization of the address after a power-on reset.

Therefore, it is recommended that the master device access the

ADP1050 at least 52 ms after a power-on reset.

If the ADP1050 is programmed to power up at this time, the soft

start ramp begins. Otherwise, the device waits for a PSON

signal, as programmed in Register 0x01 and Register 0x02.

Rev. A | Page 23 of 92

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