ADP1050ACPZ-R7 datasheet(73/93 Pages) AD

73 / 93 page

ADP1050

Data Sheet

SOFT START AND SOFTWARE RESET REGISTERS

Table 100. Register 0xFE06—Software Reset Go Command

Bits

Bit Name/Function

R/W

Description

[7:1]

Reserved

R/W

Reserved.

Software reset go

This bit lets the user perform a software reset of the ADP1050. Setting this bit resets the device

with a restart delay period from the time the ADP1050 is turned off to the time ADP1050 restarts.

The restart delay is set using Register 0xFE07[1:0] .

Table 101. Register 0xFE07—Software Reset Settings

Bits

Bit Name/Function

R/W

Description

[7:3]

Reserved

R/W

Reserved.

Additional flag reenable

delay

R/W

This bit specifies whether an additional TON_DELAY value is added to the reenable delay after a

manufacturer specific flag is cleared and before the ADP1050 begins a soft start.

0 = no additional delay is added to the reenable delay.

1 = additional delay is added to the reenable delay. The delay time is specified in the

TON_DELAY command (Register 0x60).

[1:0]

Restart delay

R/W

These bits specify the delay from the time when a PSON signal is set to the time when the soft

start begins.

Bit 1

Bit 0

Restart Delay

0 ms

500 ms

1 sec

2 sec

Table 102. Register 0xFE08—Synchronous Rectifier (SR) Soft Start Settings

Bits

Bit Name/Function

R/W

Description

Reserved

R/W

Reserved.

CS1 cycle-by-cycle current

limit to disable SR2

R/W

Setting this bit enables the CS1 cycle-by-cycle current limit to disable the SR2 output for the

remainder of the switching cycle when cycle-by-cycle current limiting occurs.

CS1 cycle-by-cycle current

limit to disable SR1

R/W

Setting this bit enables the CS1 cycle-by-cycle current limit to disable the SR1 output for the

remainder of the switching cycle when cycle-by-cycle current limiting occurs.

SR soft start setting

R/W

0 = the synchronous rectifiers perform a soft start only the first time that they are enabled.

1 = the synchronous rectifiers perform a soft start every time that they are enabled.

[3:2] SR soft start speed

R/W

When an SR PWM output is configured to turn on with soft start (using Bits [1:0]), the rising edge

of the output moves to the left in steps of 40 ns. These bits specify the number of switching

cycles that are required to move the SR PWM output in 40 ns.

Bit 3

Bit 2

SR Soft Start Timing

The SR PWM outputs change 40 ns in one switching cycle.

The SR PWM outputs change 40 ns in four switching cycles.

The SR PWM outputs change 40 ns in 16 switching cycles.

The SR PWM outputs change 40 ns in 64 switching cycles.

SR2 soft start

R/W

Setting this bit enables soft start for SR2.

SR1 soft start

R/W

Setting this bit enables soft start for SR1.

Rev. A | Page 72 of 92

ADP1050ACPZ-R7 数据表(PDF) 73 Page - Analog Devices

ADP1050ACPZ-R7 数据表(HTML) 73 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表下载

链接网址

ADP1050ACPZ-R7 数据表(PDF) 73 Page - Analog Devices

ADP1050ACPZ-R7 数据表(HTML) 73 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表 下载

链接网址

数据表下载