HC705JJ7GRSSLASHD datasheet(208/230 Pages) NXP

208 / 230 page

Electrical Speciﬁcations

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Electrical Specifications

15.6 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)

Characteristic

Symbol

Min

Typ

Max

Unit

RUN (Analog and LVR Disabled)

Internal Low-Power Oscillator at 100 kHz

Internal Low-Power Oscillator at 500 kHz

External Oscillator Running at 4.2 MHz

IDD

—

150

375

3.00

568

1100

5.20

µA

WAIT (Analog and LVR Disabled)

Internal Low-Power Oscillator at 100 kHz

Internal Low-Power Oscillator at 500 kHz

External Oscillator Running at 4.2 MHz

IDD

—

1.00

375

2.20

µA

STOP (Analog and LVR Disabled)

°C

–40

°C to 85 °C

IDD

—

µA

Incremental IDD for Enabled Modules

LVR

Analog Subsystem

IDD

—

380

475

µA

NOTES:

VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted

All values shown reflect average measurements.

Typical values at midpoint of voltage range, 25

°C only.

Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator,

all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on

OSC2.

Wait IDD is affected linearly by the OSC2 capacitance.

Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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