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HC705JJ7GRS/D 数据表(PDF) 76 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 76 Page - NXP Semiconductors

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Operating Modes
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Operating Modes
6.4.3 Halt Mode
The STOP instruction puts the MCU in halt mode if selected by the
SWAIT bit in the MOR. Halt mode is identical to wait mode, except that
a variable recovery delay occurs when the MCU exits halt mode. A
recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can
be selected by the DELAY bit in the MOR.
If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP
watchdog cannot be turned off inadvertently by a STOP instruction.
6.4.4 Data-Retention Mode
In the data-retention mode, the MCU retains RAM contents and CPU
register contents at VDD voltages as low as 2.0 Vdc. The data retention
feature allows the MCU to remain in a low-power consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in the data retention mode:
1. Drive the RESET pin to a logic zero.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data retention mode.
To take the MCU out of the data retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to a logic one.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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