HC705JJ7GRSSLASHD datasheet(82/230 Pages) NXP

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Parallel Input/Output

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Parallel Input/Output

PDIA5–PDIA0 — Port A Pulldown Inhibit Bits

Writing to these write-only bits controls the port A pulldown devices.

Reading these pulldown register A bits returns undefined data. Reset

clears bits PDIA5–PDIA0.

1 = Corresponding port A pin pulldown device turned off

0 = Corresponding port A pin pulldown device turned on if pin has

been programmed by the DDRA to be an input

7.3.4 Port A External Interrupts

The PIRQ bit in the MOR enables the PA3–PA0 pins to serve as external

interrupt pins in addition to the IRQ/VPP pin. The active interrupt state for

the PA3–PA0 pins is a logic one or a rising edge. A state of the PIRQ bit

in the MOR determines whether external interrupt inputs are edge-

sensitive only or both edge- and level-sensitive. Port A interrupts are

also interactive with each other and the IRQ/VPP pin as described in

4.6 External Interrupts.

NOTE:

When testing for external interrupts, the BIH and BIL instructions test the

voltage on the IRQ/VPP pin, not the state of the internal IRQ signal.

Therefore, BIH and BIL cannot test the port A external interrupt pins.

7.3.5 Port A Logic

When a PA0:PA5 pin is programmed as an output, reading the port bit

actually reads the value of the data latch and not the voltage on the pin

itself. When a PA0:PA5 pin is programmed as an input, reading the port

bit reads the voltage level on the pin. The data latch can always be

written, regardless of the state of its DDR bit. Figure 7-4 shows the I/O

logic of PA0:PA5 pins of port A.

The data latch can always be written, regardless of the state of its DDR

bits. Table 7-1 summarizes the operations of the port A pins.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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