HC705JJ7GRSSLASHD datasheet(100/230 Pages) NXP

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Parallel Input/Output

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Parallel Input/Output

7.5.2 Data Direction Register C (DDRC)

The contents of the port C data direction register (DDRC) determine

whether each port C pin is an input or an output. Writing a logic one to a

DDRC bit enables the output buffer for the associated port C pin. A

DDRC bit set to a logic one also disables the pulldown device for that pin.

Writing a logic zero to a DDRC bit disables the output buffer for the

associated port C pin. A reset initializes all DDRC bits to logic zeros,

configuring all port C pins as inputs.

DDRC7–DDRC0 — Port C Data Direction Bits

These read/write bits control port C data direction. Reset clears the

DDRC7–DDRC0 bits.

1 = Corresponding port C pin conﬁgured as output and pulldown

device disabled

0 = Corresponding port C pin conﬁgured as input

7.5.3 Port C Pulldown Devices

All port C pins can have software programmable pulldown devices

enabled or disabled globally by the SWPDI bit in the MOR. These

pulldown devices are individually controlled by the write-only pulldown

pins (PC7:4) and PDICL controls the lower four pins (PC3:0). Clearing

the PDICH or PDICL bits in the PDRA turns on the pulldown devices if

the port C pin is an input. Reading the PDRA returns undefined results

since it is a write-only register. Reset clears the PDICH and PDICL bits,

which turns on all the port C pulldown devices.

$0006

Bit 7

654321

Bit 0

Read:

DDRC7

DDRC6

DDRC5

DDRC4

DDRC3

DDRC2

DDRC1

DDRC0

Write:

Reset:

00000000

= Unimplemented

Figure 7-14. Data Direction Register C (DDRC)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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