HC705JJ7GRSSLASHD datasheet(95/230 Pages) NXP

95 / 230 page

Parallel Input/Output

Port B

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

When using the PB6/SDI pin, the following interactions must be noted:

1. If the SIOP function is required, then the SPE bit in the SCR must

be set. This causes the PB6/SDI pin buffer to be disabled to allow

the PB6/SDI pin to act as an input that feeds the serial data input

(SDI) of the SIOP. The pulldown device is disabled in this case.

2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6

and PB6 data register bits are still accessible to the CPU and can

be altered or read without affecting the SIOP functionality.

However, if the DDRB6 bit is cleared, reading the PB6 data

3. If the SIOP function is terminated by clearing the SPE bit in the

SCR, then the last conditions stored in the DDRB6, PDIB6, and

PB6 register bits will then control the PB6/SDI pin.

4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in

the SCR and the DDRB6 bit must be cleared. Depending on the

external application, the pulldown device may also be disabled by

setting the PDIB6 pulldown inhibit bit.

5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the

SCR must be cleared and the DDRB6 bit must be set. The

pulldown device will be disabled in this case.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 95 Page - NXP Semiconductors