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HC705JJ7GRS/D 数据表(PDF) 54 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 54 Page - NXP Semiconductors |
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54 / 230 page  Interrupts General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Interrupts components like filter capacitors and a crystal or ceramic resonator and consumes more power. The selection and enable conditions for these two oscillators are shown in Table 4-2. Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2 set is provided so that the EPO can be started and allowed to stabilize while the LPO still clocks the MCU. The reset state is for OM1 to be cleared and OM2 to be set, which selects the LPO and disables the EPO. IRQF — External Interrupt Request Flag The IRQ flag is a clearable, read-only bit that is set when an external interrupt request is pending. Writing to the IRQF bit has no effect. Reset clears the IRQF bit. 1 = Interrupt request pending 0 = No interrupt request pending The following conditions set the IRQ flag: • An external interrupt signal on the IRQ/VPP pin • An external interrupt signal on pin PA0, PA1, PA2, or PA3 when the PA0–PA3 pins are enabled by the PIRQ bit in the MOR to serve as external interrupt sources. The following conditions clear the IRQ flag: • When the CPU fetches the interrupt vector • When a logic one is written to the IRQR bit Table 4-2. Oscillator Selection OM2 OM1 Oscillator Selected by CPU Internal Low-Power Oscillator (LPO) External Pin Oscillator (EPO) Power Consumption 0 0 Internal Enabled Disabled Lowest 0 1 External Disabled Enabled Normal 1 0 Internal Enabled Disabled Lowest 1 1 Internal Enabled Enabled Normal Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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