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HC705JJ7GRS/D 数据表(PDF) 94 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 94 Page - NXP Semiconductors

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Parallel Input/Output
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
7.4.8 PB6/SDI Logic
The PB6/SDI pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-11. The operations of
PB6/SDI pin are summarized in Table 7-3.
Figure 7-11. PB6/SDI Pin I/O Circuit
DATA DIRECTION
REGISTER B
BIT DDRB6
PORT B DATA
REGISTER
BIT PB6
PULLDOWN
REGISTER B
BIT PDIB6
R
R
PB6
READ $0005
WRITE $0001
READ $0001
WRITE $0011
PULLDOWN
DEVICE
RESET
WRITE $0005
SDI
SERIAL ENABLE (SPE)
SERIAL DATA IN (SDI)
MASK OPTION REGISTER ($1FF1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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