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HC705JJ7GRS/D 数据表(PDF) 35 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 35 Page - NXP Semiconductors |
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35 / 230 page  Memory Input/Output Registers MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Memory * Features related to port C are only available on the 28-pin MC68HC705JP7 devices. Addr. Register R/W Bit 7 6 5 4 3 2 1 Bit 0 $0010 * Port A & Port C Pulldown, PDRA Read: Write: PDICH PDICL PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 $0011 Port B Pulldown, PDRB Read: Write: PDIB7 PDIB6 PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0 $0012 Timer Control, TCR Read: ICIE OCIE TOIE 000 IEDG OLVL Write: $0013 Timer Status, TSR Read: ICF OCF TOF 00000 Write: $0014 Input Capture MSB, ICRH Read: BIT15 14 13 12 11 10 9 BIT8 Write: $0015 Input Capture LSB, ICRL Read: BIT7 6 5 4 3 2 1 BIT0 Write: $0016 Output Compare MSB, OCRH Read: BIT15 14 13 12 11 10 9 BIT8 Write: $0017 Output Compare LSB, OCRL Read: BIT7 6 5 4 3 2 1 BIT0 Write: $0018 Timer Counter MSB, TMRH Read: BIT15 14 13 12 11 10 9 BIT8 Write: $0019 Timer Counter LSB, TMRL Read: BIT7 6 5 4 3 2 1 BIT0 Write: $001A Alternate. Counter MSB, ACRH Read: BIT15 14 13 12 11 10 9 BIT8 Write: $001B Alternate. Counter LSB, ACRL Read: BIT7 6 5 4 3 2 1 BIT0 Write: $001C EPROM Programming, EPROG Read: 0 0 0 0 0 ELAT MPGM EPGM Write: RRRR $001D Analog Control, ACR Read: CHG ATD2 ATD1 ICEN CPIE CP2EN CP1EN ISEN Write: $001E Analog Status, ASR Read: CPF2 CPF1 0 0 COE1 VOFF CMP2 CMP1 Write: CPFR2 CPFR1 R $001F Reserved Read: R R R R RRRR Write: R R R R RRRR = Unimplemented R = Reserved Figure 2-4. I/O Registers $0010–$001F Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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