HC705JJ7GRSSLASHD datasheet(53/230 Pages) NXP

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Interrupts

External Interrupts

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Interrupts

NOTE:

If the port A pins are enabled as external interrupts, then a high level on

any PA0:3 pin will drive the state of the IRQ function such that the

IRQ/VPP pin and other PA0:3 pins to be ignored until ALL of the PA0:3

pins have returned to a low level. Similarly, if the IRQ/VPP pin is at a low

level, the PA0:3 pins will be ignored until the IRQ/VPP pin returns to a

high state.

4.6.3 IRQ Status and Control Register (ISCR)

The IRQ status and control register (ISCR), shown in Figure 4-4,

contains an external interrupt mask (IRQE), an external interrupt flag

(IRQF), and a flag reset bit (IRQR). Unused bits will read as logic zeros.

The ISCR also contains two control bits for the oscillators, external pin

oscillator, and internal low-power oscillator. Reset sets the IRQE and

OM2 bits; and clears all the other bits.

IRQE — External Interrupt Request Enable

This read/write bit enables external interrupts. Reset sets the IRQE

bit.

1 = External interrupt processing enabled

0 = External interrupt processing disabled

OM1 and OM2 — Oscillator Selects

These bits control the selection and enabling of the oscillator source

for the MCU. One choice is the internal low-power oscillator (LPO).

The other choice is the external pin oscillator (EPO) which is common

to most MC68HC05 MCU devices. The EPO uses external

$000D

Bit 7

654321

Bit 0

Read:

IRQE

OM2

OM1

IRQF

Write:

IRQR

Reset:

110000

= Unimplemented

= Reserved

U = Unaffected

Figure 4-4. IRQ Status and Control Register (ISCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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