HC705JJ7GRSSLASHD datasheet(89/230 Pages) NXP

89 / 230 page

Parallel Input/Output

Port B

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

7.4.6 PB4/AN4/TCMP/CMP1 Logic

The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be

controlled by the OLVL bit from the output compare function of the 16-bit

programmable timer, or be controlled directly by the output of

comparator 1 as shown in Figure 7-9. The PB4 data, the programmable

timer OLVL bit, and the output of comparator 1 are all logically ORed

together to drive the pin. Also, the analog subsystem input channel 4

multiplexer is connected directly to this pin. The operations of PB4 pin

are summarized in Table 7-2.

Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit

PORT BDATA

BIT PB4

DATA DIRECTION

BIT DDRB4

PULLDOWN

BIT PDIB4

PB4

ANALOG SUBSYSTEM

INPUT AN4 AND

TIMER OUTPUT COMPARE

READ $0005

WRITE $0001

READ $0001

WRITE $0011

PULLDOWN

DEVICE

RESET

WRITE $0005

AN4

TCMP

OLVL

MASK OPTION REGISTER ($1FF1)

CMP1

(COMPARATOR 1 OUT)

(TIMER OUTPUT COMPARE)

MASK OPTION REGISTER ($1FF0)

HIGH SINK/

SOURCE CURRENT

CAPABILITY

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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