HC705JJ7GRSSLASHD datasheet(60/230 Pages) NXP

部件名	HC705JJ7GRS/D

功能描述	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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60 / 230 page

Resets

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Resets

5.2 Introduction

This section describes the five reset sources and how they initialize the

MCU. A reset immediately stops the operation of the instruction being

executed, initializes certain control bits, and loads the program counter

with a user defined reset vector address. The following conditions

produce a reset:

•

Initial power-up of device (power-on reset)

•

A logic zero applied to the RESET pin (external reset)

•

Timeout of the COP watchdog (COP reset)

•

Low voltage applied to the device (LVR reset)

•

Fetch of an opcode from an address not in the memory map

(illegal address reset)

Figure 5-1 shows a block diagram of the reset sources and their

interaction.

Figure 5-1. Reset Sources

RESET

LATCH

COP WATCHDOG

POWER-ON RESET

ILLEGAL ADDRESS RESET

INTERNAL

CLOCK

RST

TO CPU

AND

LOW-VOLTAGE RESET

VDD

3-CYCLE

CLOCKED

1-SHOT

SUBSYSTEMS

ADDRESS BUS

MASK OPTION REGISTER ($1FF1)

INTERNAL DATA BUS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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