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HC705JJ7GRS/D 数据表(PDF) 23 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 23 Page - NXP Semiconductors |
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23 / 230 page  General Description Device Options MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification General Description Figure 1-1. User Mode Block Diagram ÷2 SIMPLE SERIAL INTERFACE (SIOP) STK PTR WATCHDOG & ILLEGAL ADDR DETECT 16-BIT TIMER (1) INPUT CAPTURE (1) OUTPUT COMPARE EXTERNAL OSCILLATOR COND CODE REG 1 1 1 I N Z C H INDEX REG CPU CONTROL 0 0 0 1 1 0 0 0 0 0 RESET OSC1 OSC2 STATIC RAM (4T) — 224 BYTES ALU 68HC05 CPU ACCUM PROGRAM COUNTER CPU REGISTERS PA0*† PA1*† PA2*† PA3*† PA4* PB4/AN4/TCMP/CMP1* PB3/AN3/TCAP USER EPROM — 6160 BYTES * High sink current capability * High source current capability † IRQ interrupt capability PB2/AN2 PB1/AN1 PB0/AN0 15-STAGE CORE TIMER SYSTEM INTERNAL OSCILLATOR INT INT VSS VDD + - COMPARATOR CONTROL & MULTIPLEXER TCMP VDD CURRENT SOURCE + - COMP2 COMP1 TCAP INT PB7/SCK PB6/SDI PB5/SDO PA5* LVR OCF TOF ICF TEMPERATURE DIODE VSS PC3* PC4* PC5* PC6* PC7* PC0* PC1* PC2* PORT C ONLY ON 28-PIN VERSIONS VSS PERSONALITY EPROM — 64 BITS IRQ/VPP BOOT ROM — 240 BYTES Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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