HC705JJ7GRSSLASHD datasheet(97/230 Pages) NXP

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Parallel Input/Output

Port B

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

When using the PB7/SCK pin, the following interactions must be noted:

1. If the SIOP function is required, then the SPE bit in the SCR must

be set. This causes the PB7/SCK pin buffer to be controlled by the

MSTR control bit in the SCR. The pulldown device is disabled in

these cases.

If the MSTR bit is set, then the PB7/SCK pin buffer will be

enabled and driven by the serial data clock (SCK) from the

SIOP.

If the MSTR bit is clear, then the PB7/SCK pin buffer will be

disabled, allowing the PB7/SCK pin to drive the serial data

clock (SCK) into the SIOP.

2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7

and PB7 data register bits are still accessible to the CPU and can

be altered or read without affecting the SIOP functionality.

However, if the DDRB7 bit is cleared, reading the PB7 data

3. If the SIOP function is terminated by clearing the SPE bit in the

SCR, then the last conditions stored in the DDRB7, PDIB7, and

PB7 register bits will then control the PB7/SCK pin.

4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in

the SCR and the DDRB7 bit must be cleared. Depending on the

external application, the pulldown device may also be disabled by

setting the PDIB7 pulldown inhibit bit.

5. If the PB7/SCK pin is to be a digital output, then the SPE bit in the

SCR must be cleared and the DDRB7 bit must be set. The

pulldown device will be disabled when the pin is set as an output.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 97 Page - NXP Semiconductors