HC705JJ7GRSSLASHD datasheet(29/230 Pages) NXP

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General Description

PA0–PA5

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

General Description

applies to the I/O pins that are ORed to create the IRQ signal. For more

information, refer to 4.6 External Interrupts.

1.10 PA0–PA5

These six I/O lines comprise port A, a general-purpose bidirectional I/O

port. This port also has four pins which have keyboard interrupt

capability. All six of these pins have high current source and sink

capability.

All of these pins have software programmable pulldowns which can be

disabled by the SWPDI bit in the MOR.

1.11 PB0–PB7

These eight I/O lines comprise port B, a general-purpose bidirectional

I/O port. This port is also shared with the 16-bit programmable timer

input capture and output compare functions, with the two voltage

comparators in the analog subsystem, and with the simple serial

interface (SIOP).

The outputs of voltage comparator 1 can directly drive the PB4 pin; and

the PB4 pin has high current source and sink capability.

All of these pins have software programmable pulldowns which can be

disabled by the SWPDI bit in the MOR.

1.12 PC0–PC7 (MC68HC705JP7)

These eight I/O lines comprise port C, a general-purpose bidirectional

I/O port. This port is only available on the 28-pin MC68HC705JP7. All

eight of these pins have high current source and sink capability.

All of these pins have software programmable pulldowns which can be

disabled by the SWPDI bit in the MOR.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 29 Page - NXP Semiconductors